NXP Semiconductors SC16C750IB64,128
- Part No.:
- SC16C750IB64,128
- Manufacturer:
- NXP Semiconductors
- Package:
- 64-LQFP
- Datasheet:
-
SC16C750IB64,128.pdf
- Description:
- IC UART 64BYTE 64LQFP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SC16C750IB64,128 from NXP Semiconductors (formerly Philips) is a 64-byte FIFO Universal Asynchronous Receiver/Transmitter (UART) IC for high-speed serial data conversion in embedded communication interfaces. It supports up to 3 Mbits/s at 5 V, features auto-RTS/CTS hardware flow control, 64-byte TX/RX FIFOs with four selectable trigger levels, and operates across 2.5 V, 3.3 V, and 5 V supply rails in industrial temperature range (−40 °C to +85 °C). It is used in industrial gateways, legacy PC peripherals, and multi-channel modem systems requiring reliable asynchronous serial bridging.
For engineers reviewing the SC16C750IB64,128 datasheet, SC16C750IB64,128 pinout, SC16C750IB64,128 application, or SC16C750IB64,128 equivalent, key selection criteria include FIFO depth compatibility with host CPU interrupt latency, voltage-level alignment with system I/O, LQFP64 package footprint constraints, and register-level backward compatibility with 16C450/16C550 software stacks.
Technical Context
The SC16C750IB64,128 implements a dual-path asynchronous serial interface with independent transmitter and receiver sections, each backed by dedicated 64-byte FIFOs and programmable trigger thresholds. Its enhanced feature register (EFR) enables automatic RTS/CTS assertion based on real-time FIFO fill level, eliminating software polling overhead.
It uses a single 16× baud rate generator clocked up to 48 MHz, supporting precise baud rates from DC to 3 Mbits/s via DLL/DLM divisor latches. Internal loop-back mode, sleep mode (activated via IER[4]), and full modem control (RI, DCD, DSR, CTS, RTS, DTR) are implemented through standardized register maps compatible with legacy 16C450 drivers.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Max Data Rate | 3 Mbits/s at 5 V - enables direct connection to high-speed modems and ISDN interfaces without external rate limiting. |
| FIFO Depth | 64-byte TX + 64-byte RX - reduces CPU interrupt frequency by >95% vs. 16C450 (0-byte) and >60% vs. 16C550 (16-byte), easing real-time scheduling. |
| Supply Voltage | 2.5 V / 3.3 V / 5 V ±10% - supports mixed-voltage system integration without level shifters in industrial control backplanes. |
| Operating Temp | −40 °C to +85 °C - qualified for uncontrolled industrial environments including factory automation and outdoor telecom cabinets. |
| Interrupt Priority | Three-level prioritized ISR - ensures time-critical receive timeout and line status events preempt lower-priority modem status interrupts. |
| Baud Generator | 16× clock input up to 48 MHz - allows exact synthesis of standard rates (e.g., 115.2 kbit/s, 460.8 kbit/s) using integer divisors with zero error. |
| Flow Control | Hardware auto-RTS/CTS via EFR[6:7] - eliminates software handshaking latency and prevents FIFO overflow under burst traffic conditions. |
Pinout & Package
LQFP64 package (10 × 10 × 1.4 mm, SOT314-2); 64-pin quad flat with exposed thermal pad (not electrically connected); lead-free and RoHS compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| D0–D7 | Data Bus I/O | 8-bit bidirectional parallel interface to CPU or microcontroller; 3-state TTL-compatible for shared bus arbitration. |
| A0–A2 | Register Address | Selects among 8 internal register sets (THR/RHR, IER/ISR, FCR, LCR, MCR/MSR, LSR, SPR, DLL/DLM) during read/write cycles. |
| IOR / IOW | Read/Write Strobe | Asymmetric active-low/high strobes allow direct interfacing to Intel- or Motorola-style bus controllers without glue logic. |
| CS0–CS2 | Chip Select | 3-input decoded enable (CS0=H, CS1=H, CS2=L) permits dense multi-UART addressing in memory-mapped I/O space. |
| TX / RX | Serial I/O | Full-duplex UART channel; TX drives composite serial output with start/stop/parity framing; RX accepts TTL-level async input. |
| RTS / CTS | Flow Control | Active-low handshake signals; auto-controlled by FIFO fill level when EFR[6:7]=11b - no firmware intervention required. |
| INT | Interrupt Output | Open-drain active-high signal multiplexing up to 4 interrupt sources (RX ready, TX empty, line error, modem change) with priority encoding. |
| XTAL1 / XTAL2 | Oscillator Interface | Supports parallel-resonant crystal (1.8432–48 MHz) or external clock; XTAL2 floats in sleep mode to minimize leakage. |
| RXRDY / TXRDY | DMA Ready | Active-low DMA request signals synchronized to FIFO trigger levels - enables burst transfers without CPU cycle stealing. |
| MR | Master Reset | Asynchronous active-high reset that clears all registers and forces outputs to safe states (TX=marking, RTS/DTR=inactive). |
Key Features
| Feature | Design Value |
|---|---|
| 64-byte TX/RX FIFOs | Reduces host CPU interrupt load by enabling batched data transfers - critical for deterministic response in real-time OS environments. |
| Auto-RTS/CTS Flow Control | Hardware-managed RTS assertion at configurable FIFO thresholds (1/4/8/16/32/56 bytes) prevents overrun without driver-layer intervention. |
| Sleep Mode (IER[4]) | Cuts quiescent current to µA-range during idle periods; wakes automatically on start bit, modem pin transition, or TX data write. |
| Loop-back Diagnostics | Internal TX→RX path isolates physical layer faults; validates register access, FIFO integrity, and interrupt generation without external cabling. |
| Modem Interface Support | Full RS-232/RS-485 modem control (DTR/RTS/DCD/DSR/RI/CTS) with delta-change detection and interrupt masking per signal. |
Applications
| Industrial Serial Gateway | Legacy PC Peripheral Bridge |
|---|---|
|
Use Scenario: Aggregating Modbus RTU, ASCII, and custom protocols from field devices into Ethernet or CAN backbone. IC Role / Device Role / Timing Role: UART interface IC handling protocol framing, parity checking, and hardware flow control between MCU and RS-485 transceivers. Use Value: 64-byte FIFOs absorb burst traffic from multiple sensors while maintaining <100 µs interrupt latency - essential for sub-second control loops. |
Use Scenario: Enabling ISA/PCI-based industrial PCs to communicate with older CNC machines, barcode scanners, and PLCs via RS-232. IC Role / Device Role / Timing Role: Drop-in replacement for 16C550 UARTs in motherboard super I/O chips, preserving BIOS and DOS driver compatibility. Use Value: Pin- and register-compatible with TL16C750 and ST16C450, allowing hardware reuse while doubling FIFO depth for improved throughput. |
| Multi-Channel Modem System | Telecom Line Card Interface |
|
Use Scenario: Supporting simultaneous dial-up connections in VoIP gateways or remote access servers with integrated analog modems. IC Role / Device Role / Timing Role: High-speed serial controller managing TX/RX data paths, modem status monitoring, and auto-handshake signaling for up to 8 channels. Use Value: 3 Mbits/s capability and independent TX/RX trigger levels enable concurrent 56k modem sessions without CPU bottlenecks. |
Use Scenario: Interfacing digital signal processors (DSPs) to T1/E1 line interface units (LIUs) in carrier-grade access equipment. IC Role / Device Role / Timing Role: Asynchronous framing engine converting parallel DSP command/status words into serial control streams for LIU configuration. Use Value: Sleep mode and false start-bit rejection ensure robust operation in noisy telecom environments with minimal power draw during standby. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar UART applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TL16C750IPN | Same 64-byte FIFO, identical pinout (LQFP64), but rated only for 5 V operation and lacks 2.5 V/3.3 V support. | Restricted to 5 V-only systems; not suitable for mixed-voltage or low-power industrial designs. | Select TL16C750IPN only if legacy 5 V bus architecture prohibits voltage scaling and full SC16C750IB64,128 feature set is unnecessary. |
| ST16C750BQ | 64-byte FIFO, 3.3 V/5 V operation, but no sleep mode and limited auto-flow control granularity (only two RTS trigger levels vs. six). | Higher static power in always-on deployments; less responsive to variable-rate modem traffic due to coarse flow threshold resolution. | Choose ST16C750BQ where cost sensitivity outweighs power efficiency and fine-grained flow control requirements. |
Compared with TL16C750IPN and ST16C750BQ, the SC16C750IB64,128 uniquely delivers triple-voltage operation, six-step auto-RTS trigger levels, and hardware sleep mode - making it the only option meeting full industrial power, flexibility, and interoperability requirements.
Availability
SC16C750IB64,128 is available at Aetrix Electronics and suitable for industrial serial gateways, legacy PC peripheral bridges, multi-channel modem systems, and telecom line card interfaces requiring stable component supply across extended product lifecycles.
Supply support for SC16C750IB64,128 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors, formerly Philips Semiconductors, is a global leader in high-performance mixed-signal ICs for automotive, industrial, and communication applications.
The SC16C750IB64,128 belongs to NXP's legacy UART product line designed for robust, long-lifecycle serial interface solutions in industrial control, telecom infrastructure, and embedded computing platforms.
FAQ
What is the maximum data rate supported by the SC16C750IB64,128?
The SC16C750IB64,128 supports up to 3 Mbits/s at 5 V supply, 2 Mbits/s at 3.3 V, and 1 Mbit/s at 2.5 V. This is achieved using a 48 MHz external clock input divided by 16 in the baud rate generator. The actual achievable rate depends on crystal accuracy, PCB layout, and transceiver loading - verified in the SC16C750IB64,128 datasheet Section 6.5.
Does the SC16C750IB64,128 support automatic hardware flow control?
Yes, the SC16C750IB64,128 supports full automatic hardware flow control via its Enhanced Feature Register (EFR). When EFR[6] (RTS) and EFR[7] (CTS) are set to 1, the device autonomously asserts RTS based on receive FIFO fill level and suspends transmission when CTS is deasserted - all without CPU intervention. This behavior is documented in SC16C750IB64,128 datasheet Section 6.3.
Is the SC16C750IB64,128 pin-compatible with older UARTs like the 16C450?
Yes, the SC16C750IB64,128 is pin-compatible with the TL16C750 and powers up functionally equivalent to the 16C450. Its LQFP64 footprint matches industry-standard layouts, and register mapping preserves backward compatibility with existing 16C450 drivers - confirmed in SC16C750IB64,128 datasheet Section 1 and Table 3.
How does the sleep mode operate in the SC16C750IB64,128?
Sleep mode in the SC16C750IB64,128 is enabled by setting IER[4] = 1. The device enters low-power state until awakened by a start bit on RX, modem pin transition (RI/DCD/DSR/CTS), or TX data write. Upon wake, it resumes normal operation and re-enters sleep after final character transmission or reception - detailed in SC16C750IB64,128 datasheet Section 6.7.
What package type is used for the SC16C750IB64,128?
The SC16C750IB64,128 uses a plastic low-profile quad flat package (LQFP64) with 64 leads, 10 mm × 10 mm body size, and 1.4 mm height (SOT314-2). This package is specified in SC16C750IB64,128 ordering information Table 1 and supports standard reflow soldering profiles.
SC16C750IB64,128 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 64-LQFP
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Features:
- -
- Number of Channels:
- 1, UART
- FIFO's:
- 64 Byte
- Protocol:
- -
- Data Rate (Max):
- 3Mbps
- Voltage - Supply:
- 2.5V, 3.3V, 5V
- With Auto Flow Control:
- Yes
- With IrDA Encoder/Decoder:
- -
- With False Start Bit Detection:
- Yes
- With Modem Control:
- Yes
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 64-LQFP (10x10)
SC16C750IB64,128 FAQ
1.How can I place an order for SC16C750IB64,128 through Aetrix?
Please submit a Request for Quotation (RFQ) for SC16C750IB64,128 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SC16C750IB64,128 reliable?
The price and inventory of SC16C750IB64,128 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SC16C750IB64,128 is usually 5 days.
3.What payment methods are accepted for SC16C750IB64,128?
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4.How is shipping managed for SC16C750IB64,128?
SC16C750IB64,128 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SC16C750IB64,128 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SC16C750IB64,128?
For technical support, including SC16C750IB64,128 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SC16C750IB64,128 requirements.
6.How does Aetrix verify that SC16C750IB64,128 is sourced from the original manufacturer or authorized distributors?
All SC16C750IB64,128 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SC16C750IB64,128 meets industry standards.
7.What is the process for return or replacement of SC16C750IB64,128?
All SC16C750IB64,128 units undergo pre-shipment inspection (PSI). If there is an issue with SC16C750IB64,128, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SC16C750IB64,128 part is unused and in its original packaging.
Return procedure for SC16C750IB64,128:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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