My Inquiry
My Account
NXP Semiconductors SC16C752BIBS,128
- Part No.:
- SC16C752BIBS,128
- Manufacturer:
- NXP Semiconductors
- Package:
- 32-VFQFN Exposed Pad
- Datasheet:
-
SC16C752BIBS,128.pdf
- Description:
- IC DUAL UART 64BYTE 32HVQFN
- Quantity:
- Payment:
- Shipping:
Inventory:3,390
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SC16C752BIBS,128 from NXP Semiconductors is a dual-channel UART IC with 64-byte transmit/receive FIFOs, hardware/software flow control, and up to 5 Mbit/s data rate at 3.3 V/5 V operation - used in industrial serial communication gateways requiring high-throughput, low-interrupt overhead RS-232/RS-485 interface bridging.
For engineers reviewing the SC16C752BIBS,128 datasheet, SC16C752BIBS,128 pinout, SC16C752BIBS,128 application, or SC16C752BIBS,128 equivalent, key selection considerations include FIFO trigger programmability, auto-RTS/CTS timing control via TCR register, dual-channel interrupt prioritization, and HVQFN32 package compatibility with space-constrained embedded controllers.
Technical Context
The SC16C752BIBS,128 implements two independent UART channels (A and B) sharing an 8-bit parallel bus, each with dedicated TX/RX shift registers, 64-byte FIFOs with error flagging, and fully prioritized six-level interrupt architecture. Its enhanced feature register (EFR) enables auto-RTS/CTS, Xon/Xoff programmability, and special character detection.
It supports programmable baud rates via 16-bit divisor with prescaler (÷4), operates across 2.5 V–5 V supply, and delivers false start bit detection, line break generation/detection, and internal loopback for diagnostics - all while maintaining pin and software compatibility with SC16C752 and TL16C752.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Channels | Dual independent UARTs (A and B) - enables simultaneous serial links without external multiplexing. |
| Max Data Rate | 5 Mbit/s at 3.3 V or 5 V - supports high-speed industrial protocols like Modbus RTU over RS-485. |
| FIFO Depth | 64-byte TX + 64-byte RX per channel - reduces CPU interrupt load by >90% vs. 16-byte FIFO UARTs. |
| Flow Control | Hardware (auto-RTS/CTS) and software (Xon/Xoff) - eliminates overrun errors in asymmetric data paths. |
| Supply Voltage | 2.5 V, 3.3 V, and 5 V operation - interoperable with mixed-voltage legacy and modern MCU systems. |
| Operating Temp | −40 °C to +85 °C - qualified for industrial automation and outdoor telemetry equipment. |
| Package | HVQFN32 (5 × 5 × 0.85 mm) - thermal-enhanced, leadless footprint for compact PCB layouts. |
Pinout & Package
HVQFN32 package: plastic thermal-enhanced very thin quad flat package, 32 terminals, body size 5 × 5 × 0.85 mm, exposed thermal pad (pin 32 = GND).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A2 | Address select inputs | Select internal register address (0–7) during I/O read/write cycles via parallel bus. |
| CSA / CSB | Channel-select chip enables | Enable UART A or B independently - allows shared bus access without address decoding logic. |
| TXA / TXB | Transmit outputs | Serial output signals for channels A and B - compatible with RS-232/RS-485 transceivers. |
| RXA / RXB | Receive inputs | Serial input signals - support local loopback mode for self-test without external wiring. |
| RTSA / RTSB | Request-to-send outputs | Auto-controlled RTS signals - deasserted when RX FIFO reaches halt level (TCR[3:0]). |
| CTSA / CTSB | Clear-to-send inputs | Hardware flow control inputs - pause transmission if CTS goes HIGH before stop bit midpoint. |
| INTA / INTB | Interrupt outputs | Active-HIGH prioritized interrupts - indicate RX/TX ready, errors, modem status, or Xoff events. |
| TXRDYA / TXRDYB | Transmit-ready flags | Active-LOW signals - assert when TX FIFO has ≥ trigger-level space, enabling DMA initiation. |
| RXRDYA / RXRDYB | Receive-ready flags | Active-LOW signals - assert when RX FIFO contains ≥1 byte or reaches trigger level. |
| D0–D7 | 8-bit bidirectional data bus | Parallel interface to host MCU - supports 8080/6800 bus timing with IOR/IOW strobes. |
| RESET | Asynchronous reset input | Active-HIGH signal - clears all registers except DLL/DLM/XON/XOFF values; sets TX/RX pins HIGH. |
| XTAL1 / XTAL2 | Crystal oscillator interface | Supports 1–25 MHz crystal or external clock - generates baud base clock with programmable prescaler. |
Key Features
| Feature | Design Value |
|---|---|
| Programmable FIFO trigger levels | Independent RX/TX thresholds via FCR and TLR - enables precise DMA alignment and interrupt latency tuning. |
| Auto-RTS with configurable halt/resume | Halt (TCR[3:0]) and resume (TCR[7:4]) levels - prevents RX FIFO overflow without host intervention. |
| Enhanced software flow control | Configurable Xon1/Xon2/Xoff1/Xoff2 tokens and Xon Any mode - supports legacy protocol compliance and robust pause/resume. |
| Complete status reporting in Sleep mode | All error flags (OE/FE/PE/BI), RXRDY/TXRDY, and modem status remain readable - enables low-power monitoring. |
| Internal loopback and false start detection | On-chip diagnostic path isolates PHY layer faults; detects invalid start bits - accelerates field failure root cause analysis. |
Applications
| Industrial Serial Gateway | Medical Device Interface |
|---|---|
Use Scenario: Aggregating data from multiple RS-485 sensors (temperature, pressure, flow) into a single ARM-based controller running Linux. IC Role / Device Role / Timing Role: Dual UART bridges two isolated serial buses; 64-byte FIFOs absorb burst traffic from sensor polling cycles without CPU saturation. Use Value: Reduces average interrupt frequency from ~12 kHz to <1.5 kHz per channel, freeing CPU cycles for real-time analytics. | Use Scenario: Connecting ECG monitor front-end ASIC to host microcontroller via isolated RS-232 link with strict EMC requirements. IC Role / Device Role / Timing Role: UART A handles patient data streaming; UART B manages configuration commands and firmware updates. Use Value: Auto-RTS/CTS coordination prevents data loss during high-priority command execution, meeting IEC 62304 Class C timing constraints. |
| POS Terminal Backplane | Smart Energy Meter Hub |
Use Scenario: Integrating barcode scanner, receipt printer, and magnetic stripe reader into a single payment terminal motherboard. IC Role / Device Role / Timing Role: SC16C752BIBS,128 provides three concurrent serial interfaces via channel A/B and shared bus arbitration. Use Value: Hardware flow control eliminates print buffer underruns and scanner timeout errors during concurrent peripheral access. | Use Scenario: Communicating with PLCs, smart meters, and RF mesh nodes in AMI (Advanced Metering Infrastructure) concentrator units. IC Role / Device Role / Timing Role: Dual UART manages primary HAN (Home Area Network) and backup WAN (Wide Area Network) modems simultaneously. Use Value: Programmable 5–8 bit word length and 1/1.5/2 stop bits ensures interoperability with legacy metering protocols (DLMS/COSEM, ANSI C12.18). |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual UART applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TL16C752BIPTR | Same dual UART architecture, 64-byte FIFOs, and pinout - but rated only for 3 V–3.6 V operation; no 2.5 V or 5 V support. | Limited to 3.3 V-only systems; cannot replace SC16C752BIBS,128 in mixed-voltage or legacy 5 V designs. | Select when operating exclusively at 3.3 V and cost sensitivity outweighs voltage flexibility. |
| SC16C752BIB48 | Identical electrical specs and register set - differs only in LQFP48 package (7 × 7 × 1.4 mm) versus HVQFN32 (5 × 5 × 0.85 mm). | Requires PCB redesign due to larger footprint and different thermal pad layout; not suitable for space-constrained modules. | Choose for prototyping or where thermal mass or hand-soldering preference favors LQFP. |
Compared with TL16C752BIPTR and SC16C752BIB48, the SC16C752BIBS,128 uniquely combines 2.5 V–5 V operation with HVQFN32's compact thermal profile - making it optimal for next-gen industrial edge nodes where board area and supply voltage headroom are both constrained.
Availability
SC16C752BIBS,128 is available at Aetrix Electronics and suitable for industrial serial gateways, medical device interfaces, POS terminal backplanes, smart energy meter hubs, and embedded telemetry systems requiring stable component supply and long-term lifecycle assurance.
Supply support for SC16C752BIBS,128 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT applications - delivering high-reliability interface, power, and security ICs.
The SC16C752BIBS,128 belongs to NXP's legacy industrial UART product line, designed specifically for robust, low-overhead serial bridging in harsh environments where deterministic latency and error resilience are critical.
FAQ
What is the maximum baud rate supported by the SC16C752BIBS,128?
The SC16C752BIBS,128 supports up to 5 Mbit/s at 3.3 V or 5 V operation. At 2.5 V supply, the maximum achievable baud rate is 3 Mbit/s. This performance is enabled by its high-speed internal clock divider and optimized transmitter/receiver logic - verified under industrial temperature conditions (−40 °C to +85 °C). The SC16C752BIBS,128 achieves this using a programmable 16-bit divisor with optional prescaler (÷4), allowing precise rate matching for protocols like RS-485 half-duplex timing.
Does the SC16C752BIBS,128 support hardware flow control on both UART channels?
Yes, the SC16C752BIBS,128 supports independent hardware flow control on both UART A and UART B channels via dedicated RTSn/CTSn pins. Auto-RTS and auto-CTS functions are individually enabled through the Enhanced Feature Register (EFR[7:6]), and their trigger thresholds are configured via the Transmission Control Register (TCR). This allows channel-specific flow control behavior - for example, enabling auto-RTS on UART A for sensor data ingestion while disabling it on UART B for command-response telemetry.
How does the SC16C752BIBS,128 handle receive FIFO overflow errors?
The SC16C752BIBS,128 prevents receive FIFO overflow through coordinated auto-RTS signaling and interrupt-driven servicing. When the RX FIFO reaches the halt level (programmed in TCR[3:0]), RTSn is de-asserted to pause the remote transmitter. If overflow occurs despite this, the Line Status Register (LSR[1]) sets the Overrun Error (OE) flag, which persists until all erroneous characters are read from the FIFO. The SC16C752BIBS,128 also provides RXRDYn status and prioritized interrupts to ensure timely servicing - critical for deterministic industrial communication.
Can the SC16C752BIBS,128 operate from a 2.5 V supply?
Yes, the SC16C752BIBS,128 is fully specified for 2.5 V, 3.3 V, and 5 V operation. At 2.5 V, it maintains full functionality including 64-byte FIFOs, hardware/software flow control, and interrupt generation - though maximum data rate is reduced to 3 Mbit/s. Input pins D0–D7, A0–A2, CSA/CSB, IOR/IOW, RESET, and XTAL1 are 5 V tolerant, enabling safe interfacing with higher-voltage peripherals even when powered at 2.5 V.
What package type is used for the SC16C752BIBS,128?
The SC16C752BIBS,128 uses the HVQFN32 package: a plastic thermal-enhanced very thin quad flat package with 32 terminals, body dimensions of 5 × 5 × 0.85 mm, and an exposed thermal pad (pin 32 = GND). This package offers superior thermal dissipation over standard QFN variants and is optimized for high-density PCB layouts in space-constrained industrial modules - confirmed in NXP's ordering information table (SOT617-1).
SC16C752BIBS,128 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 32-VFQFN Exposed Pad
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Features:
- -
- Number of Channels:
- 2, DUART
- FIFO's:
- 64 Byte
- Protocol:
- -
- Data Rate (Max):
- 5Mbps
- Voltage - Supply:
- 2.5V, 3.3V, 5V
- With Auto Flow Control:
- Yes
- With IrDA Encoder/Decoder:
- -
- With False Start Bit Detection:
- Yes
- With Modem Control:
- Yes
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-HVQFN (5x5)
SC16C752BIBS,128 FAQ
1.How can I place an order for SC16C752BIBS,128 through Aetrix?
Please submit a Request for Quotation (RFQ) for SC16C752BIBS,128 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SC16C752BIBS,128 reliable?
The price and inventory of SC16C752BIBS,128 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SC16C752BIBS,128 is usually 5 days.
3.What payment methods are accepted for SC16C752BIBS,128?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SC16C752BIBS,128 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SC16C752BIBS,128?
SC16C752BIBS,128 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SC16C752BIBS,128 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SC16C752BIBS,128?
For technical support, including SC16C752BIBS,128 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SC16C752BIBS,128 requirements.
6.How does Aetrix verify that SC16C752BIBS,128 is sourced from the original manufacturer or authorized distributors?
All SC16C752BIBS,128 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SC16C752BIBS,128 meets industry standards.
7.What is the process for return or replacement of SC16C752BIBS,128?
All SC16C752BIBS,128 units undergo pre-shipment inspection (PSI). If there is an issue with SC16C752BIBS,128, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SC16C752BIBS,128 part is unused and in its original packaging.
Return procedure for SC16C752BIBS,128:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SC16C752BIBS,128 Tags
-
SC16IS741AIPWJ
NXP Semiconductors
-
TL16C550CPTR
Texas Instruments
-
TL16C550CIPTR
Texas Instruments
-
SC16C752BIB48,128
NXP Semiconductors
-
ST16C2550CQ48-F
MaxLinear, Inc.
-
ST16C2550CJ44-F
MaxLinear, Inc.
-
ST16C2552CJ44-F
MaxLinear, Inc.
-
ST16C1550IQ48-F
MaxLinear, Inc.
-
ST16C2550IQ48-F
MaxLinear, Inc.
-
ST16C554DIQ64-F
MaxLinear, Inc.
-
ST16C554DCQ64-F
MaxLinear, Inc.
-
XR17V352IB113-F
MaxLinear, Inc.
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
