NXP Semiconductors SC16C752IB48,157
- Part No.:
- SC16C752IB48,157
- Manufacturer:
- NXP Semiconductors
- Package:
- 48-LQFP
- Datasheet:
-
SC16C752IB48,157.pdf
- Description:
- IC DUAL UART 64BYTE 48LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:3,370
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Product details
Overview
SC16C752IB48,157 from NXP Semiconductors (formerly Philips) is a dual-channel UART IC with independent 64-byte transmit and receive FIFOs, hardware/software flow control, and support for data rates up to 5 Mbit/s at 3.3 V or 5 V. It integrates full modem control (RTS/CTS/DSR/DTR/RI/CD), programmable baud rate generation, and DMA-ready TXRDY/RXRDY signaling - deployed in industrial serial gateways, embedded communication controllers, and legacy RS-232/RS-485 interface modules.
For engineers reviewing the SC16C752IB48,157 datasheet, SC16C752IB48,157 pinout, SC16C752IB48,157 application, or SC16C752IB48,157 equivalent, key selection considerations include FIFO trigger level programmability (via TCR/TLR), Auto-RTS/Auto-CTS timing behavior, sleep mode entry conditions, Xon/Xoff character configuration flexibility, and LQFP48 package compatibility with legacy SC16C2550-based PCB layouts.
Technical Context
The SC16C752IB48,157 implements two fully independent UART channels (A and B), each with dedicated 64-byte FIFOs, separate interrupt outputs (INTA/INTB), and individual chip select (CSA/CSB) and modem control lines. Its enhanced feature register (EFR) enables Auto-RTS/CTS, Xon/Xoff software flow control, and sleep mode activation - all configurable without external logic.
It uses a 16× oversampling baud rate generator with prescaler (÷1 or ÷4) and divisor (1–65535), supporting precise rate derivation from XTAL1/XTAL2 or external clock input. Interrupt prioritization covers six levels including receiver line status, RX timeout, THR empty, modem status, Xoff detection, and CTS/RTS edge events - all reported via IIR with automatic clearing on read or condition resolution.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Channels | Dual independent UARTs (A and B) with separate registers, interrupts, and modem signals. |
| FIFO depth | 64-byte TX and RX FIFO per channel - reduces CPU interrupt load and supports burst transfers. |
| Max data rate | 5 Mbit/s at 3.3 V or 5 V supply - enables high-speed serial links in industrial PLCs and protocol converters. |
| Flow control | Hardware (Auto-RTS/CTS) and software (programmable Xon1/Xon2/Xoff1/Xoff2) - eliminates overrun/underrun in asymmetric traffic. |
| Supply voltage | 2.5 V, 3.3 V, and 5 V operation - allows direct integration into mixed-voltage legacy and modern systems. |
| Interrupt system | Six prioritized interrupt sources with individual enable bits and IIR-encoded type reporting - simplifies real-time ISR dispatching. |
| Sleep mode | Enabled via EFR[4] + IER[4]; halts internal clocks when RX idle, TX FIFO empty, and no pending non-THR interrupts - cuts dynamic power significantly. |
Pinout & Package
SC16C752IB48,157 is housed in a plastic LQFP48 package (7 × 7 × 1.4 mm, SOT313-2) with 48 leads and exposed pad not electrically connected.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A2 | Address select inputs | Select internal register address (0–7) during IOR/IOW cycles; required for accessing UART A/B control/status registers. |
| CSA / CSB | Channel-select chip enables | Active-LOW enables register access to UART A or B independently - supports shared bus arbitration without address decoding logic. |
| TXA/TXB, RXA/RXB | Serial data I/O | Full-duplex asynchronous serial channels A and B; TTL-level compatible; support local loop-back for diagnostics. |
| RTSA/RTSB, CTSA/CTSB | Hardware flow control | Auto-RTS asserts LOW when RX FIFO space available; Auto-CTS deassertion halts TX - prevents FIFO overflow without software intervention. |
| INTA / INTB | Per-channel interrupt outputs | Active-HIGH open-drain capable; individually maskable via IER - enables concurrent servicing of two serial streams in RTOS environments. |
| TXRDYA/TXRDYB, RXRDYA/RXRDYB | DMA handshake signals | Active-LOW flags indicating TX FIFO space or RX FIFO occupancy ≥ trigger level - directly interfaces with DMA controllers for zero-CPU-transfer bursts. |
| XTAL1 / XTAL2 | Clock input/output | Supports crystal (1–25 MHz) or external clock source; internal oscillator forms timing reference for baud rate generator and internal logic. |
Key Features
| Feature | Design Value |
|---|---|
| Programmable FIFO trigger levels | Independent RX/TX trigger thresholds (via FCR and TLR) optimize interrupt/DMA efficiency for varying latency requirements. |
| Enhanced Auto-RTS timing control | Halt/resume levels stored in TCR[3:0]/TCR[7:4] allow precise RX FIFO watermarking - prevents data loss during flow handshaking. |
| Multi-character Xon/Xoff support | Configurable dual-token detection (Xon1/Xon2, Xoff1/Xoff2) increases robustness against false flow-control character matches in noisy environments. |
| Modem status register mirroring | Real-time reflection of CDA/DSRA/RIA/CDA states in MSR - enables host software to monitor remote device readiness without polling GPIOs. |
| False start bit detection | Rejects spurious leading edges on RX line - improves reliability in electrically noisy industrial serial networks. |
Applications
| Industrial Serial Gateway | Legacy Equipment Interface |
|---|---|
Use Scenario: Aggregating data from multiple RS-232 field devices (sensors, meters, HMIs) into a single Ethernet or CAN backbone. IC Role / Device Role / Timing Role: Dual UART bridges asynchronous serial protocols to a central microcontroller; each channel handles one device stream with independent flow control and error reporting. Use Value: 64-byte FIFOs absorb bursty sensor reports; Auto-RTS/CTS prevents overrun when gateway CPU is busy; dual INT outputs enable parallel interrupt handling. | Use Scenario: Retrofitting modern microcontrollers into aging CNC machines or medical analyzers that rely on fixed-baud RS-232 control interfaces. IC Role / Device Role / Timing Role: Protocol-transparent UART translator between legacy 8-bit bus peripherals and new ARM-based controllers; maintains exact timing and framing expected by original firmware. Use Value: Pin compatibility with SC16C2550 allows drop-in replacement; programmable baud generator replicates legacy 9600/19200/38400 rates; sleep mode reduces standby power in always-on equipment. |
| Embedded Modem Controller | Multi-Port Terminal Server |
Use Scenario: Managing POTS or cellular modems in remote telemetry units where AT command parsing, carrier detection, and line status monitoring are critical. IC Role / Device Role / Timing Role: Full modem interface controller - monitors CTS/DSR/RI/CD inputs and drives RTS/DTR outputs while buffering command/response traffic in FIFOs. Use Value: Dedicated modem status register (MSR) provides instantaneous line state visibility; ring indicator (RI) edge-triggered interrupt enables fast call detection; carrier detect (CD) flag supports auto-answer logic. | Use Scenario: Providing four simultaneous serial console ports (two per UART channel) for network switch/router debugging and out-of-band management. IC Role / Device Role / Timing Role: Dual-channel UART with shared 8-bit data bus and independent CS/INT lines - enables compact multi-port design using single peripheral bus. Use Value: TXRDY/RXRDY signals drive DMA for zero-copy console logging; FIFO RDY register allows single read to poll TXRDY/RXRDY status across both channels - minimizes bus overhead. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual UART applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SC16C2550IB48,112 | Lacks 64-byte FIFO (16-byte only), no Auto-RTS/CTS, no sleep mode, no TCR/TLR registers - baseline feature set. | Lower interrupt/DMA efficiency; unsuitable for high-throughput or low-power designs requiring advanced flow control. | Select only when cost sensitivity outweighs performance needs and existing PCB layout mandates pin compatibility without enhanced features. |
| MAX3100EAP+T | Single-channel SPI-interface UART; 128-byte FIFO; integrated ±15 kV ESD protection; operates at 2.7–5.5 V. | No native parallel bus interface; requires SPI master; lacks modem control pins (RTS/CTS/DSR/DTR/RI/CD); no Auto-RTS/CTS logic. | Choose for space-constrained SPI-based systems needing higher ESD tolerance and deeper FIFO, but accept trade-off of losing parallel bus simplicity and full modem functionality. |
Compared with SC16C2550IB48,112, the SC16C752IB48,157 delivers higher throughput and lower CPU load via larger FIFOs and hardware flow control; versus MAX3100EAP+T, it retains legacy parallel bus compatibility and complete modem signaling - making it optimal for industrial retrofit and multi-device serial aggregation.
Availability
SC16C752IB48,157 is available at Aetrix Electronics and suitable for industrial serial gateways, legacy equipment interface modules, and embedded modem controllers requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant sourcing.
Supply support for SC16C752IB48,157 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT applications - formed from the spin-off of Philips Semiconductors in 2006.
The SC16C752IB48,157 belongs to NXP's legacy UART product line, designed specifically for robust, pin-compatible upgrades of 16550/16C2550-based systems in industrial automation and communications infrastructure.
FAQ
What is the maximum supported baud rate for SC16C752IB48,157?
The SC16C752IB48,157 supports up to 5 Mbit/s at 3.3 V or 5 V supply voltage. At 2.5 V operation, the maximum data rate is reduced to 3 Mbit/s. This limit is defined by internal timing margins and applies to both UART channels independently under specified VCC and temperature conditions.
Does SC16C752IB48,157 support hardware flow control with Auto-RTS and Auto-CTS?
Yes, SC16C752IB48,157 supports independent Auto-RTS and Auto-CTS functions enabled via bits EFR[6] and EFR[7]. Auto-RTS deasserts when the RX FIFO reaches the halt level (TCR[3:0]) and reasserts at the resume level (TCR[7:4]); Auto-CTS gates transmission based on CTS input state - both reduce host CPU overhead in high-speed serial links.
How does the sleep mode function in SC16C752IB48,157?
SC16C752IB48,157 enters sleep mode when EFR[4] and IER[4] are set, and three conditions hold: RX line is idle (HIGH for 4 char times), TX FIFO and shift register are empty, and no pending interrupts exist except THR or timeout. Sleep mode stops internal clocks to reduce power; wake-up occurs on RX edge, modem pin change, or TX FIFO write.
Can SC16C752IB48,157 be used as a direct replacement for SC16C2550IB48,112?
Yes, SC16C752IB48,157 is pin-compatible with SC16C2550IB48,112 and shares identical LQFP48 footprint and parallel bus interface. However, enhanced features (64-byte FIFO, Auto-RTS/CTS, TCR/TLR, sleep mode) require updated firmware initialization - no hardware changes are needed, but software must configure EFR and related registers to unlock full capability.
What are the valid character formats supported by SC16C752IB48,157?
SC16C752IB48,157 supports 5-, 6-, 7-, or 8-bit data words; even, odd, or no parity; and 1, 1.5, or 2 stop bits - all configured per channel via the Line Control Register (LCR). These settings apply identically to both UART A and B, and are retained across reset except for LCR default value (0x1D).
SC16C752IB48,157 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 48-LQFP
- Series:
- -
- Packaging:
- Tray
- Product Status:
- Obsolete
- Features:
- -
- Number of Channels:
- 2, DUART
- FIFO's:
- 64 Byte
- Protocol:
- -
- Data Rate (Max):
- 5Mbps
- Voltage - Supply:
- 2.5V, 3.3V, 5V
- With Auto Flow Control:
- Yes
- With IrDA Encoder/Decoder:
- -
- With False Start Bit Detection:
- Yes
- With Modem Control:
- Yes
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 48-LQFP (7x7)
SC16C752IB48,157 FAQ
1.How can I place an order for SC16C752IB48,157 through Aetrix?
Please submit a Request for Quotation (RFQ) for SC16C752IB48,157 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SC16C752IB48,157 reliable?
The price and inventory of SC16C752IB48,157 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SC16C752IB48,157 is usually 5 days.
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Once your SC16C752IB48,157 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SC16C752IB48,157?
For technical support, including SC16C752IB48,157 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SC16C752IB48,157 requirements.
6.How does Aetrix verify that SC16C752IB48,157 is sourced from the original manufacturer or authorized distributors?
All SC16C752IB48,157 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SC16C752IB48,157 meets industry standards.
7.What is the process for return or replacement of SC16C752IB48,157?
All SC16C752IB48,157 units undergo pre-shipment inspection (PSI). If there is an issue with SC16C752IB48,157, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SC16C752IB48,157 part is unused and in its original packaging.
Return procedure for SC16C752IB48,157:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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