NXP Semiconductors SC16C852LIBS,115
- Part No.:
- SC16C852LIBS,115
- Manufacturer:
- NXP Semiconductors
- Package:
- 32-VFQFN Exposed Pad
- Datasheet:
-
SC16C852LIBS,115.pdf
- Description:
- IC UART DUAL W/FIFO 32-HVQFN
- Quantity:
- Payment:

- Shipping:

Inventory:3,812
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SC16C852LIBS,115 from NXP Semiconductors is a 1.8 V dual-channel UART IC supporting up to 5 Mbit/s serial data rates, featuring 128-byte transmit/receive FIFOs, IrDA 1.0 encoder/decoder, and selectable Intel (16-mode) or Motorola (68-mode) bus interface. It operates across −40 °C to +85 °C and targets industrial embedded systems requiring high-throughput, low-power asynchronous communication with modem control and RS-485 support.
For engineers reviewing the SC16C852LIBS,115 datasheet, SC16C852LIBS,115 pinout, SC16C852LIBS,115 application, or SC16C852LIBS,115 equivalent, key selection considerations include dual-channel concurrent operation, programmable 128-level FIFO trigger thresholds, automatic RS-485 driver turn-around with delay, hardware/software flow control, and HVQFN32 package compatibility with thermal pad requirements.
Technical Context
The SC16C852LIBS,115 implements two independent UART channels with fully separate register sets, baud rate generators, and FIFO control logic. Each channel supports programmable start/stop/parity framing, local loopback diagnostics, and interrupt-driven or DMA-based data transfer using TXRDYx/RXRDYx handshaking signals.
Its extended mode enables 128-byte FIFO operation via dedicated TXINTLVL/RXINTLVL registers, while the clock prescaler (0–15, 1/16-step granularity) allows precise non-standard baud rate synthesis from an 80 MHz input clock or crystal oscillator. RS-485 address detection and turn-around timing are controlled through AFCR1/RS485TIME registers.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 1.8 V nominal - enables direct integration into low-voltage SoC subsystems without level-shifting. |
| Max Data Rate | 5 Mbit/s - achievable with 80 MHz external clock; supports high-speed modem and networking interfaces. |
| FIFO Depth | 128-byte TX/RX per channel - reduces CPU interrupt load and improves throughput in multi-channel environments. |
| Bus Interface | Selectable Intel 16-mode or Motorola 68-mode - software-configurable via 16/68 pin; supports legacy and modern host architectures. |
| IrDA Support | Version 1.0 at ≤115.2 kbit/s - integrated encoder/decoder eliminates external transceiver components. |
| Operating Temp | −40 °C to +85 °C - qualified for industrial-grade deployment in harsh ambient conditions. |
| RS-485 Features | Automatic address detection & programmable turn-around delay - simplifies half-duplex bus arbitration without firmware overhead. |
Pinout & Package
SC16C852LIBS,115 is housed in a 32-terminal HVQFN package (5 mm × 5 mm × 0.85 mm body, SOT617-1) with exposed thermal pad. The pad must be soldered to a PCB thermal pad with vias for electrical grounding and thermal dissipation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A2 | Address select inputs | Decode internal register addresses during 16-mode bus access; A3 used in 68-mode for channel selection. |
| CSA/CSB or CS/A3 | Chip select / channel address | In 16-mode: CSA enables UART-A, CSB enables UART-B; in 68-mode: CS enables both, A3 selects channel. |
| TXA/TXB, RXA/RXB | Serial I/O | Dual independent full-duplex UART channels; support RS-232, RS-485, and IrDA physical layers. |
| TXRDYA/TXRDYB, RXRDYA/RXRDYB | DMA handshake outputs | Active-low ready signals indicating FIFO occupancy status for DMA controller synchronization. |
| RTSA/RTSB, CTSA/CTSB | Hardware flow control | Standard modem control pins enabling automatic RTS/CTS handshaking per channel. |
| 16/68 | Bus interface mode select | Logic HIGH (or unconnected) configures Intel 16-bit interface; LOW selects Motorola 68k-style interface. |
| LOWPWR | Low-power enable input | Active-HIGH signal disables oscillator and isolates host bus to reduce quiescent current during idle periods. |
| XTAL1/XTAL2 | Clock input/output | Supports crystal (≤1.5 Mbit/s) or external clock (≤80 MHz) for flexible baud rate generation. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-channel concurrent write | Enables simultaneous register writes to both UART-A and UART-B via shared data bus, improving configuration efficiency. |
| 128 programmable FIFO trigger levels | Allows fine-grained tuning of interrupt/DMA activation points per channel, optimizing CPU utilization and latency trade-offs. |
| Automatic RS-485 turn-around | Hardware-managed driver direction switching with user-defined delay eliminates timing-critical firmware delays. |
| Independent TX/RX baud rate generators | Permits asymmetric communication (e.g., different speeds on transmit vs. receive) for protocol bridging applications. |
| Enhanced Sleep mode | Reduces power consumption by gating clocks and isolating bus drivers while preserving FIFO contents and register state. |
Applications
| Industrial PLC Communication | Medical Device Serial Gateway |
|---|---|
Use Scenario: Connecting multiple fieldbus devices (Modbus RTU over RS-485) to a central controller in factory automation. IC Role / Device Role / Timing Role: Dual UART handles concurrent RS-485 master/slave polling and diagnostics traffic with automatic driver turn-around. Use Value: Eliminates external RS-485 transceivers and timing-critical firmware delays via integrated turn-around control and 128-byte FIFO buffering. | Use Scenario: Aggregating serial data streams from ECG, SpO₂, and infusion pump modules into a central display unit. IC Role / Device Role / Timing Role: SC16C852LIBS,115 acts as a low-power, isolated serial concentrator with IrDA and RS-232 support. Use Value: 1.8 V operation and enhanced sleep mode extend battery life; 128-byte FIFOs prevent data loss during CPU interrupts. |
| Embedded Network Router | Test Equipment Control Interface |
Use Scenario: Providing console and management port connectivity in compact edge routers with limited PCB area. IC Role / Device Role / Timing Role: Dual UART delivers simultaneous CLI access (UART-A) and out-of-band management (UART-B) over separate physical interfaces. Use Value: HVQFN32 footprint saves board space; 5 Mbit/s capability supports fast firmware updates and debug logging. | Use Scenario: Interfacing automated test equipment (ATE) with DUTs requiring precise serial command sequencing and response capture. IC Role / Device Role / Timing Role: SC16C852LIBS,115 serves as a deterministic, low-jitter serial controller with hardware flow control and loopback diagnostics. Use Value: Independent TX/RX baud rate generators enable protocol translation; internal loopback validates link integrity pre-test. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual UART applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SC16C752IBS,115 | Same 1.8 V dual UART architecture but lacks IrDA encoder/decoder and RS-485 turn-around timer. | Suitable for RS-232-only or non-IrDA applications where cost sensitivity outweighs feature set. | Select when IrDA and RS-485 features are unnecessary and lower BOM cost is prioritized. |
| TI TL16C752BPTR | 3.3 V operation, 64-byte FIFOs, no IrDA, no RS-485 auto-turn-around; pinout incompatible with SC16C852LIBS,115. | Targeted at legacy 3.3 V systems with moderate throughput needs and standard modem control only. | Choose only if migrating from TI-based designs and voltage/FIFO/IrDA requirements are relaxed. |
Compared with SC16C752IBS,115 and TL16C752BPTR, the SC16C852LIBS,115 delivers higher FIFO depth, integrated IrDA, and hardware RS-485 timing-enabling single-chip solutions for space-constrained, multi-protocol industrial gateways without external logic or transceivers.
Availability
SC16C852LIBS,115 is available at Aetrix Electronics and suitable for industrial PLC communication, medical device serial gateways, embedded network routers, and test equipment control interfaces requiring stable component supply and long-term lifecycle support.
Supply support for SC16C852LIBS,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT applications.
The SC16C852LIBS,115 belongs to NXP's high-performance UART product line, designed specifically for industrial embedded systems demanding robust serial communication, low-voltage operation, and advanced protocol support including RS-485 and IrDA.
FAQ
What is the maximum serial data rate supported by the SC16C852LIBS,115?
The SC16C852LIBS,115 supports up to 5 Mbit/s when driven by an 80 MHz external clock. With a crystal oscillator, the maximum rate is 1.5 Mbit/s. These limits are defined by the internal baud rate generator architecture and timing margins specified in the NXP datasheet Rev. 4. The SC16C852LIBS,115 achieves this performance while maintaining full 128-byte FIFO functionality and error detection capabilities.
Does the SC16C852LIBS,115 support both RS-232 and RS-485 physical layers?
The SC16C852LIBS,115 provides UART logic and protocol handling but does not include integrated line drivers or receivers. It supports RS-232 and RS-485 through external transceivers connected to its TXA/RXA and TXB/RXB pins. Its built-in RS-485 features-including automatic address detection and programmable turn-around delay-are specifically designed to simplify interface with RS-485 transceivers like the MAX3080 or SN65HVD72.
How does the LOWPWR pin function on the SC16C852LIBS,115?
The LOWPWR pin on the SC16C852LIBS,115 is an active-HIGH input that places the device into low-power mode by shutting off the internal oscillator and isolating host bus interface pins (A0–A2, D0–D7, CSA/CSB, etc.) from the external bus. When LOWPWR is de-asserted (goes LOW), the device resets automatically, restoring all registers to default states. An internal pull-down resistor allows the pin to be left unconnected for normal operation.
Is the SC16C852LIBS,115 pin-compatible with the SC16C652B in the same package?
Yes - the SC16C852LIBS,115 is pin-, function-, and software-compatible with the SC16C652B when both are in the LQFP48 package (SC16C852LIB). However, the SC16C852LIBS,115 uses the HVQFN32 package, which has a different pin count and layout. Pin compatibility does not extend across packages; the HVQFN32 variant requires a new PCB layout and cannot serve as a drop-in replacement for SC16C652B in LQFP48.
What are the thermal requirements for the HVQFN32 package of the SC16C852LIBS,115?
The SC16C852LIBS,115 in HVQFN32 (SOT617-1) requires connection of the exposed center thermal pad to a PCB copper pour with thermal vias for reliable operation. Per NXP documentation, the VSS pin and the exposed pad must both be connected to system ground. Failure to solder the thermal pad may cause overheating, reduced reliability, or functional instability under sustained 5 Mbit/s operation. Thermal design guidelines are detailed in the "PCB Layout Recommendations" section of the datasheet.
SC16C852LIBS,115 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 32-VFQFN Exposed Pad
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Features:
- -
- Number of Channels:
- 2, DUART
- FIFO's:
- 128 Byte
- Protocol:
- RS485
- Data Rate (Max):
- 5Mbps
- Voltage - Supply:
- 1.8V
- With Auto Flow Control:
- Yes
- With IrDA Encoder/Decoder:
- Yes
- With False Start Bit Detection:
- Yes
- With Modem Control:
- Yes
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-HVQFN (5x5)
SC16C852LIBS,115 FAQ
1.How can I place an order for SC16C852LIBS,115 through Aetrix?
Please submit a Request for Quotation (RFQ) for SC16C852LIBS,115 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SC16C852LIBS,115 reliable?
The price and inventory of SC16C852LIBS,115 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SC16C852LIBS,115 is usually 5 days.
3.What payment methods are accepted for SC16C852LIBS,115?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SC16C852LIBS,115 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SC16C852LIBS,115?
SC16C852LIBS,115 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SC16C852LIBS,115 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SC16C852LIBS,115?
For technical support, including SC16C852LIBS,115 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SC16C852LIBS,115 requirements.
6.How does Aetrix verify that SC16C852LIBS,115 is sourced from the original manufacturer or authorized distributors?
All SC16C852LIBS,115 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SC16C852LIBS,115 meets industry standards.
7.What is the process for return or replacement of SC16C852LIBS,115?
All SC16C852LIBS,115 units undergo pre-shipment inspection (PSI). If there is an issue with SC16C852LIBS,115, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SC16C852LIBS,115 part is unused and in its original packaging.
Return procedure for SC16C852LIBS,115:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SC16C852LIBS,115 Tags

-
SC16IS741AIPWJ
NXP Semiconductors

-
TL16C550CPTR
Texas Instruments

-
TL16C550CIPTR
Texas Instruments

-
SC16C752BIB48,128
NXP Semiconductors

-
ST16C2550CQ48-F
MaxLinear, Inc.

-
ST16C2550CJ44-F
MaxLinear, Inc.

-
ST16C2552CJ44-F
MaxLinear, Inc.

-
ST16C1550IQ48-F
MaxLinear, Inc.

-
ST16C2550IQ48-F
MaxLinear, Inc.

-
ST16C554DIQ64-F
MaxLinear, Inc.

-
ST16C554DCQ64-F
MaxLinear, Inc.
-
XR17V352IB113-F
MaxLinear, Inc.
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

