NXP Semiconductors SC16IS741IPW,128
- Part No.:
- SC16IS741IPW,128
- Manufacturer:
- NXP Semiconductors
- Category:
- Controllers
- Package:
- 16-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
SC16IS741IPW,128.pdf
- Description:
- IC UART 16TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:2,043
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SC16IS741IPW,128 from NXP Semiconductors is a single-channel UART IC with I²C-bus or SPI slave interface, enabling protocol conversion between I²C/SPI and RS-232/RS-485 physical layers. It delivers up to 5 Mbit/s data rate, features 64-byte TX/RX FIFOs, supports 3.3 V or 2.5 V operation, and draws <30 μA in sleep mode - making it ideal for battery-powered industrial communication gateways.
For engineers reviewing the SC16IS741IPW,128 datasheet, SC16IS741IPW,128 pinout, SC16IS741IPW,128 application, or SC16IS741IPW,128 equivalent, key selection criteria include dual-interface flexibility (I²C/SPI), automatic RS-485 direction control via RTS, IrDA SIR support, hardware/software flow control, and 16C450 register compatibility for legacy software porting.
Technical Context
The SC16IS741IPW,128 implements a fully programmable UART core with independent transmitter and receiver enable control, internal loopback mode, and a 16× clock baud rate generator using XTAL1/XTAL2 or external clock input. Its register set mirrors the 16C450 architecture, ensuring drop-in software compatibility while adding enhanced features like TCR/TLR-triggered FIFO interrupt levels and EFR-controlled Xon/Xoff detection logic.
It operates exclusively as an I²C-bus slave (up to 400 kbit/s fast-mode) or SPI slave (Mode 0), with interface selection determined by the logic level on the dedicated I2C/SPI pin. The device integrates automatic RTS/CTS handshaking, IrDA encoder/decoder interface, and configurable sleep entry conditions tied to RX idle state, TX FIFO emptiness, and pending interrupt status.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Data Rate | Up to 5 Mbit/s in 16× clock mode - enables high-speed serial bridging without CPU overhead. |
| FIFO Depth | 64 bytes TX + 64 bytes RX - reduces host interrupt frequency and improves burst data handling. |
| Supply Voltage | 2.5 V or 3.3 V - supports dual-voltage system integration with no level-shifting required. |
| Sleep Current | <30 μA at 3.3 V - extends battery life in portable and remote sensor nodes. |
| Temperature Range | −40 °C to +95 °C - qualified for industrial automation and factory floor deployment. |
| Interface Options | I²C-bus slave (400 kbit/s) or SPI slave (Mode 0) - selectable via I2C/SPI pin; no firmware reconfiguration needed. |
| RS-485 Support | Automatic driver direction control via RTS signal - eliminates external transceiver control logic. |
Pinout & Package
TSSOP16 package (SOT403-1), 4.4 mm body width, 0.65 mm pitch - optimized for compact PCB layouts in handheld and embedded modules.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD (Pin 1) | Power supply | Primary 2.5 V or 3.3 V supply rail; decoupling required near pin. |
| CS/A0 (Pin 2) | Interface select / address bit | SPI chip select (active LOW) or I²C address bit A0 - determines base I²C address when I2C/SPI = HIGH. |
| SI/A1 (Pin 3) | Data input / address bit | SPI serial input or I²C address bit A1 - used with A0 to configure one of four I²C addresses. |
| SO (Pin 4) | SPI data output | 3-stateable SPI MISO; undefined and must be left unconnected in I²C mode. |
| SCL/SCLK (Pin 5) | Clock input | Shared I²C SCL or SPI SCLK input - Schmitt-triggered for noise immunity. |
| SDA (Pin 6) | I²C bidirectional data | Open-drain I²C data line; must connect to VSS in SPI mode. |
| IRQ (Pin 7) | Interrupt output | Open-drain active-LOW interrupt; requires external pull-up (1 kΩ @ 3.3 V). |
| I2C/SPI (Pin 8) | Interface mode select | Logic HIGH = I²C mode; LOW = SPI mode - hardwired at power-up, not runtime configurable. |
| VSS (Pin 9) | Ground | Digital ground reference; separate analog ground not required. |
| RTS (Pin 10) | Request-to-send control | Active-LOW RTS output; drives RS-485 transceiver DE/RE pins automatically when auto RTS enabled. |
| CTS (Pin 11) | Clear-to-send input | Active-LOW CTS input; halts transmission when deasserted if auto CTS enabled. |
| TX (Pin 12) | UART transmit output | CMOS-level serial output; disabled during local loopback mode. |
| RX (Pin 13) | UART receive input | CMOS-level serial input; disabled during local loopback mode. |
| RESET (Pin 14) | Hardware reset | Active-LOW asynchronous reset; initializes registers except DLL/DLH/XON/XOFF values. |
| XTAL1 (Pin 15) | Crystal/clock input | Connects to crystal (with XTAL2) or external clock source - sets baud rate reference. |
| XTAL2 (Pin 16) | Crystal/clock output | Crystal oscillator output; forms resonant circuit with XTAL1 when crystal used. |
Key Features
| Feature | Design Value |
|---|---|
| 16C450 register compatibility | Enables direct reuse of existing UART driver code without modification or abstraction layer. |
| Auto RS-485 direction control | Eliminates need for external GPIO or timing logic to manage transceiver DE/RE signals. |
| Programmable Xon/Xoff characters | Supports single/dual-character software flow control with configurable detection logic in EFR. |
| Independent TX/RX FIFO enable | Allows asymmetric buffer usage - e.g., enable RX FIFO for burst reception while disabling TX FIFO for polled transmission. |
| IrDA SIR encoder/decoder interface | Direct connection to IrDA physical layer transceivers without additional protocol translation logic. |
| Software-initiated reset | Resets UART state and registers (except DLL/DLH/XON/XOFF) without requiring hardware RESET pin assertion. |
Applications
| Industrial PLC Gateway | Battery-Powered Data Logger |
|---|---|
Use Scenario: Connecting legacy RS-485 field devices (sensors, actuators) to a modern I²C-based microcontroller in a compact DIN-rail mounted controller. IC Role / Device Role / Timing Role: Protocol bridge converting I²C commands from MCU into RS-485 frames, managing RTS-driven transceiver direction and hardware flow control with CTS. Use Value: Reduces BOM count by eliminating discrete level shifters and direction-control logic; 64-byte FIFO prevents data loss during MCU interrupt latency. | Use Scenario: Remote environmental monitoring node powered by coin-cell battery, transmitting sensor readings over RS-232 to a cellular modem. IC Role / Device Role / Timing Role: Low-power UART interface between MCU and modem, entering sleep mode when idle and waking on RX activity or TX FIFO write. Use Value: Sleep current <30 μA extends operational lifetime to multi-year intervals; IrDA SIR interface allows optional optical diagnostics without extra IC. |
| Cellular IoT Modem Interface | Factory Automation HMI Adapter |
Use Scenario: Integrating AT-command-capable LTE module into an ARM Cortex-M4 host using SPI for minimal pin count and deterministic timing. IC Role / Device Role / Timing Role: SPI slave UART providing full-duplex AT command channel with hardware flow control to prevent command buffer overflow in modem. Use Value: SPI Mode 0 compatibility ensures seamless integration with most MCUs; auto CTS prevents dropped AT responses during high-throughput data sessions. | Use Scenario: Adding serial debug and configuration port to a touch HMI panel using RS-232 for technician access via laptop. IC Role / Device Role / Timing Role: I²C slave UART translating host I²C writes into RS-232 TX and buffering incoming RS-232 RX into 64-byte FIFO for efficient polling. Use Value: I²C-bus slave operation frees MCU GPIOs; 16C450 register map allows use of standard Linux ttySx drivers without custom kernel module. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar UART bridge applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SC16IS752IPW,128 | Dual-channel UART with identical I²C/SPI interface, same TSSOP16 package, but higher pin count due to second UART set (TX2/RX2/RTS2/CTS2). | Required when two independent serial links (e.g., RS-232 debug + RS-485 field bus) must coexist on one I²C/SPI bus. | Select SC16IS752IPW,128 only if dual UART functionality is needed; SC16IS741IPW,128 offers lower cost and smaller footprint for single-link designs. |
| MAX3107ETJ+ | Single UART with SPI-only interface (no I²C), 128-byte FIFOs, integrated ±15 kV ESD protection on TX/RX, but no automatic RS-485 direction control or IrDA interface. | Suitable for SPI-only systems requiring higher ESD robustness and deeper buffers, but lacks RS-485 auto-direction and I²C compatibility. | Choose MAX3107ETJ+ when ESD protection and larger FIFOs outweigh need for I²C support and RS-485 driver control. |
Compared with SC16IS741IPW,128, the SC16IS752IPW,128 adds channel density at the cost of pin count and layout complexity, while the MAX3107ETJ+ trades I²C flexibility and RS-485 integration for higher ESD rating and deeper buffers - making SC16IS741IPW,128 optimal for cost-sensitive, space-constrained I²C-based RS-485 gateways.
Availability
SC16IS741IPW,128 is available at Aetrix Electronics and suitable for industrial PLC gateways, battery-powered data loggers, cellular IoT modem interfaces, and factory automation HMI adapters requiring stable component supply across extended product lifecycles.
Supply support for SC16IS741IPW,128 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT applications.
The SC16IS741IPW,128 belongs to NXP's SC16IS7xx family of intelligent UART bridges, designed specifically to simplify serial interface expansion in resource-constrained embedded systems using I²C or SPI host buses.
FAQ
What interface protocols does the SC16IS741IPW,128 support?
The SC16IS741IPW,128 supports I²C-bus slave mode (up to 400 kbit/s) and SPI slave mode (Mode 0) - selected permanently at power-up via the I2C/SPI pin. It does not support master-mode operation or UART-to-UART bridging. The SC16IS741IPW,128 uses these interfaces to receive commands and data from a host processor and convert them to RS-232/RS-485 serial streams.
Does the SC16IS741IPW,128 require an external crystal?
The SC16IS741IPW,128 can operate with either a crystal (connected between XTAL1 and XTAL2) or an external clock source applied to XTAL1. No crystal is mandatory - a precision clock generator or MCU-derived clock may be used. The SC16IS741IPW,128's baud rate generator divides this input to produce the 16× clock needed for serial timing.
How does automatic RS-485 direction control work on the SC16IS741IPW,128?
The SC16IS741IPW,128 asserts RTS (active LOW) when the RX FIFO has space and deasserts it when the FIFO reaches the halt trigger level - directly driving the DE/RE pins of an RS-485 transceiver. This behavior is enabled via EFR[6] and requires no host intervention. The SC16IS741IPW,128 also supports RTS polarity inversion for transceivers with inverted enable logic.
Is the SC16IS741IPW,128 compatible with legacy 16C450 software drivers?
Yes - the SC16IS741IPW,128 implements a register map fully backward-compatible with the industry-standard 16C450 UART, including identical offsets for RHR, THR, IER, FCR, LCR, MCR, LSR, and MSR. Software written for 16C450 or its derivatives (e.g., 16550A) runs unchanged on the SC16IS741IPW,128, with enhanced features accessible via extended registers (EFR, TCR, TLR).
What is the minimum sleep current of the SC16IS741IPW,128?
The SC16IS741IPW,128 achieves a sleep current of less than 30 μA at 3.3 V when EFR[4] and IER[4] are set and all wake conditions (RX activity, modem pin change, TX FIFO write) are inactive. This ultra-low quiescent draw makes the SC16IS741IPW,128 suitable for energy-harvesting and long-life battery applications where periodic wake-up events dominate power budgeting.
SC16IS741IPW,128 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 16-TSSOP (0.173", 4.40mm Width)
- Programmable:
- Not Verified
- Protocol:
- RS232, RS485
- Function:
- Controller
- Interface:
- I2C, SPI, UART
- Standards:
- -
- Voltage - Supply:
- 2.5V, 3.3V
- Current - Supply:
- 6mA
- Operating Temperature:
- -40°C ~ 95°C
- Supplier Device Package:
- 16-TSSOP
- Grade:
- -
- Qualification:
- -
SC16IS741IPW,128 FAQ
1.How can I place an order for SC16IS741IPW,128 through Aetrix?
Please submit a Request for Quotation (RFQ) for SC16IS741IPW,128 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SC16IS741IPW,128 reliable?
The price and inventory of SC16IS741IPW,128 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SC16IS741IPW,128 is usually 5 days.
3.What payment methods are accepted for SC16IS741IPW,128?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SC16IS741IPW,128 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SC16IS741IPW,128?
SC16IS741IPW,128 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SC16IS741IPW,128 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SC16IS741IPW,128?
For technical support, including SC16IS741IPW,128 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SC16IS741IPW,128 requirements.
6.How does Aetrix verify that SC16IS741IPW,128 is sourced from the original manufacturer or authorized distributors?
All SC16IS741IPW,128 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SC16IS741IPW,128 meets industry standards.
7.What is the process for return or replacement of SC16IS741IPW,128?
All SC16IS741IPW,128 units undergo pre-shipment inspection (PSI). If there is an issue with SC16IS741IPW,128, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SC16IS741IPW,128 part is unused and in its original packaging.
Return procedure for SC16IS741IPW,128:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SC16IS741IPW,128 Tags

-
PTN5150AHXMP
NXP Semiconductors

-
USB3740B-AI9-TR
Microchip Technology

-
USB3740B-AI2-TR
Microchip Technology

-
USB3300-EZK-TR
Microchip Technology

-
USB3300-EZK
Microchip Technology

-
FUSB340TMX
onsemi

-
FUSB302BMPX
onsemi

-
DP83826IRHBR
Texas Instruments

-
MCP2518FDT-E/QBB
Microchip Technology

-
FUSB302MPX
onsemi

-
MCP2518FDT-E/SL
Microchip Technology

-
FT260Q-R
FTDI, Future Technology Devices International Ltd
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

