NXP Semiconductors SC16IS750IPW,112
- Part No.:
- SC16IS750IPW,112
- Manufacturer:
- NXP Semiconductors
- Category:
- Controllers
- Package:
- 24-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
SC16IS750IPW,112.pdf
- Description:
- IC UART I2C/SPI 24-TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SC16IS750IPW,112 from NXP Semiconductors is a single-channel UART IC with dual I²C-bus/SPI interface, 64-byte TX/RX FIFOs, IrDA SIR support up to 115.2 kbit/s, and 8 programmable GPIOs. It operates at 2.5 V or 3.3 V, supports baud rates up to 5 Mbit/s, and targets RS-232/RS-485 protocol conversion in battery-powered industrial gateways.
For engineers reviewing the SC16IS750IPW,112 datasheet, SC16IS750IPW,112 pinout, SC16IS750IPW,112 application, or SC16IS750IPW,112 equivalent, key selection criteria include SPI clock speed limit (4 Mbit/s), TSSOP24 package compatibility, GPIO multiplexing options (DSR/DTR/CD/RI), automatic RS-485 direction control via RTS, and register-level backward compatibility with 16C450.
Technical Context
The SC16IS750IPW,112 implements a full-duplex UART core with fully programmable serial framing (5–8 data bits, 1–2 stop bits, even/odd/no parity) and an integrated baud rate generator dividing a crystal or external clock by divisors from 1 to 65535. Its interrupt architecture delivers seven prioritized sources-including RX FIFO timeout, modem status changes, and Xoff detection-with IRQ output active-low and open-drain.
FIFO operation supports independent trigger level configuration for transmit and receive paths via FCR or programmable TLR registers; auto hardware flow control uses RTS/CTS signals with configurable halt/resume thresholds in TCR; IrDA SIR encoding/decoding is handled internally without host CPU intervention.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Interface | Selectable I²C-bus (400 kbit/s max) or SPI (4 Mbit/s max); I2C/SPI pin selects mode at power-up |
| UART Channels | Single full-duplex UART with 64-byte TX and RX FIFOs; reduces host polling overhead |
| Baud Rate Range | Up to 5 Mbit/s in 16× clock mode; supports high-speed industrial serial links |
| Supply Voltage | 2.5 V or 3.3 V operation; compatible with modern low-voltage microcontrollers and FPGAs |
| GPIO Pins | 8 programmable I/O pins (GPIO0–GPIO7), configurable as DSR/DTR/CD/RI with internal pull-ups |
| IrDA Support | Built-in IrDA SIR encoder/decoder supporting 115.2 kbit/s; no external transceiver required |
| Operating Temp | −40 °C to +95 °C industrial range; validated for factory automation and outdoor edge nodes |
Pinout & Package
TSSOP24 package (SOT355-1): plastic thin shrink small outline, 24 leads, 4.4 mm body width, lead pitch 0.65 mm. Exposed pad not present - standard gull-wing leads only.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (XTAL2) | Crystal oscillator output | Drives external crystal connected between XTAL1 and XTAL2; enables self-contained timing |
| 2 (XTAL1) | Crystal input / external clock input | Accepts 1–25 MHz crystal or buffered system clock; determines UART baud accuracy |
| 4 (RESET) | Hardware reset input (active LOW) | Asynchronous reset clears all registers except DLL/DLH/XON1/XON2/XOFF1/XOFF2 |
| 5 (RX) | UART receiver input | Accepts RS-232/RS-485 logic-level serial data; disabled during local loopback mode |
| 6 (TX) | UART transmitter output | Drives RS-232/RS-485 line drivers; output disabled during local loopback |
| 7 (CTS) | Clear-to-send input (active LOW) | Controls transmit enable when auto CTS enabled in EFR[7]; status readable in MSR[4] |
| 8 (I2C/SPI) | Interface select input | HIGH = I²C mode; LOW = SPI mode; latched at power-up or reset |
| 9 (CS/A0) | SPI chip select / I²C address bit A0 | Active-LOW SPI CS; or LSB of 7-bit I²C slave address (A0+A1 define base address) |
| 10 (SI/A1) | SPI data input / I²C address bit A1 | Serial data input in SPI mode; MSB of I²C slave address when I2C/SPI = HIGH |
| 11 (SO) | SPI data output | 3-stateable output; undefined in I²C mode - must be left unconnected |
| 12 (SCL/SCLK) | I²C clock / SPI clock input | 400 kbit/s max for I²C; 4 Mbit/s max for SPI; Schmitt-triggered input |
| 13 (SDA) | I²C data I/O (open-drain) | Open-drain bidirectional bus; must be pulled up externally; undefined in SPI mode |
| 14 (IRQ) | Interrupt request output (open-drain, active LOW) | Signals pending interrupts per IIR; requires 1 kΩ pull-up to VDD at 3.3 V |
| 15–18, 20–23 (GPIO0–GPIO3, GPIO4/DSR–GPIO7/RI) | Programmable I/O pins | Configurable as general-purpose inputs/outputs or modem control signals via IOControl register |
| 24 (RTS) | Request-to-send output (active LOW) | Indicates RX FIFO readiness; controls RS-485 driver direction when auto RTS enabled in EFR[6] |
Key Features
| Feature | Design Value |
|---|---|
| Backward-compatible register map | Fully matches 16C450 layout - enables drop-in software porting from legacy UART platforms |
| Auto RS-485 direction control | RTS signal directly manages half-duplex bus driver state - eliminates external logic or timing delays |
| Independent TX/RX FIFO triggers | Configurable via FCR or TLR - allows fine-grained interrupt tuning for real-time latency control |
| Software reset capability | Host-initiated reset via register write - avoids board-level reset signal routing constraints |
| Low-power sleep mode | <30 μA at 3.3 V - extends battery life in portable diagnostics and handheld HMI devices |
| Programmable special character detection | XON/XOFF characters (single/dual) and custom special character - enables robust flow control in noisy environments |
Applications
| Industrial Serial Gateway | Portable Diagnostic Tool |
|---|---|
|
Use Scenario: Protocol translation between I²C-based MCU and legacy RS-485 fieldbus sensors in PLC backplanes. IC Role / Device Role / Timing Role: UART bridge with automatic RTS-controlled RS-485 direction switching and 64-byte buffering to absorb burst traffic. Use Value: Eliminates need for discrete level shifters and direction logic; 5 Mbit/s baud supports high-resolution sensor streaming. |
Use Scenario: Handheld medical device communicating with Bluetooth-enabled ECG module via UART. IC Role / Device Role / Timing Role: Low-power serial interface with IrDA SIR support for optical pairing and firmware updates. Use Value: Built-in IrDA encoder/decoder removes external transceiver; 30 μA sleep current extends battery runtime beyond 48 hours. |
| Factory Automation Controller | Smart Energy Meter Interface |
|
Use Scenario: Adding isolated RS-232 debug port to ARM-based motion controller using existing I²C bus. IC Role / Device Role / Timing Role: I²C-target UART with 16C450 register compatibility enabling reuse of Linux ttyS driver stack. Use Value: Reduces firmware development time; GPIO pins repurposed as DTR/DSR for modem handshaking with cellular telemetry. |
Use Scenario: Secure metering module requiring tamper-resistant UART communication with secure element IC. IC Role / Device Role / Timing Role: UART with programmable XON/XOFF flow control and special character detection for command authentication. Use Value: Prevents buffer overflow under heavy load; custom XOFF detection enables encrypted session termination handshake. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar UART bridge applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SC16IS760IPW | Supports 15 Mbit/s SPI clock (vs. 4 Mbit/s) and IrDA SIR up to 1.152 Mbit/s (vs. 115.2 kbit/s) | Required for high-throughput SPI hosts or IrDA MIR-compliant systems; otherwise functionally identical | Choose SC16IS760IPW only if SPI bandwidth >4 Mbit/s or IrDA speed >115.2 kbit/s is mandatory |
| MAX3107ETJ+ | 3.3 V only (no 2.5 V support); SPI-only interface; no IrDA; 128-byte FIFOs | Better suited for high-FIFO-depth SPI-only designs; lacks I²C option and IrDA SIR functionality | Select MAX3107ETJ+ when maximum FIFO depth and SPI simplicity outweigh need for dual-interface flexibility |
Compared with SC16IS750IPW,112, SC16IS760IPW offers higher SPI throughput and faster IrDA, while MAX3107ETJ+ trades interface flexibility for deeper FIFOs and tighter SPI integration - making SC16IS750IPW,112 optimal for cost-sensitive, dual-protocol, low-power industrial bridges.
Availability
SC16IS750IPW,112 is available at Aetrix Electronics and suitable for industrial serial gateways, portable diagnostic tools, factory automation controllers, and smart energy meter interfaces requiring stable component supply across extended product lifecycles.
Supply support for SC16IS750IPW,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT applications, with deep expertise in mixed-signal and interface IP.
The SC16IS750IPW,112 belongs to NXP's SC16IS7xx UART bridge family, designed specifically to simplify protocol conversion between embedded processors and legacy serial peripherals in space-constrained, low-power systems.
FAQ
What interface modes does the SC16IS750IPW,112 support?
The SC16IS750IPW,112 supports two mutually exclusive interface modes: I²C-bus (up to 400 kbit/s) and SPI (up to 4 Mbit/s), selected by the logic level on the I2C/SPI pin at power-up or reset. It operates exclusively as a target/slave device in both modes - no master functionality is implemented. The SC16IS750IPW,112 does not support UART-to-UART bridging or asynchronous host-side arbitration.
Does the SC16IS750IPW,112 require an external crystal?
The SC16IS750IPW,112 requires either a crystal (1–25 MHz) connected between XTAL1 and XTAL2, or a buffered external clock applied to XTAL1 - no internal RC oscillator is provided. Crystal startup time must be accounted for before UART use; after power-on reset, the host must wait ≥3 μs before register access, and longer if relying on crystal oscillation stability. The SC16IS750IPW,112 cannot operate UART functions without a valid clock source on XTAL1.
How many GPIOs does the SC16IS750IPW,112 provide, and what are their capabilities?
The SC16IS750IPW,112 provides eight dedicated GPIO pins (GPIO0–GPIO7), each with internal active pull-up resistors and configurable I/O direction via the IO Direction register. GPIO4–GPIO7 can be remapped to modem control functions (DSR/DTR/CD/RI) using the IOControl register. All GPIOs support change-of-state interrupt generation (enabled via IOIntEna register), and their states are retained across software resets but cleared on hardware reset.
Can the SC16IS750IPW,112 be used for RS-485 half-duplex communication?
Yes - the SC16IS750IPW,112 supports automatic RS-485 half-duplex direction control using its RTS output signal. When auto RTS is enabled in the Enhanced Feature Register (EFR[6]), RTS asserts (goes LOW) when the RX FIFO has sufficient space and deasserts when the FIFO reaches the configured halt threshold. This directly drives external RS-485 transceiver DE/RE pins, eliminating timing-critical external logic. The SC16IS750IPW,112 does not integrate RS-485 drivers - external transceivers remain required.
Is the SC16IS750IPW,112 pin-compatible with other devices in the SC16IS7xx family?
The SC16IS750IPW,112 shares identical pinout and package (TSSOP24) with SC16IS760IPW, enabling direct PCB footprint reuse. However, it is not pin-compatible with SC16IS740IPW (TSSOP16, 16-pin) or HVQFN24 variants (SC16IS750IBS). Functionally, SC16IS750IPW,112 and SC16IS760IPW differ only in SPI clock speed (4 vs. 15 Mbit/s) and IrDA SIR rate (115.2 kbit/s vs. 1.152 Mbit/s) - all registers, GPIOs, and interface behavior are identical.
SC16IS750IPW,112 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 24-TSSOP (0.173", 4.40mm Width)
- Programmable:
- Not Verified
- Protocol:
- RS232, RS485
- Function:
- Controller
- Interface:
- I2C, SPI, UART
- Standards:
- -
- Voltage - Supply:
- 2.5V, 3.3V
- Current - Supply:
- 6mA
- Operating Temperature:
- -40°C ~ 95°C
- Supplier Device Package:
- 24-TSSOP
- Grade:
- -
- Qualification:
- -
SC16IS750IPW,112 FAQ
1.How can I place an order for SC16IS750IPW,112 through Aetrix?
Please submit a Request for Quotation (RFQ) for SC16IS750IPW,112 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SC16IS750IPW,112 reliable?
The price and inventory of SC16IS750IPW,112 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SC16IS750IPW,112 is usually 5 days.
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Once your SC16IS750IPW,112 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SC16IS750IPW,112?
For technical support, including SC16IS750IPW,112 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SC16IS750IPW,112 requirements.
6.How does Aetrix verify that SC16IS750IPW,112 is sourced from the original manufacturer or authorized distributors?
All SC16IS750IPW,112 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SC16IS750IPW,112 meets industry standards.
7.What is the process for return or replacement of SC16IS750IPW,112?
All SC16IS750IPW,112 units undergo pre-shipment inspection (PSI). If there is an issue with SC16IS750IPW,112, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SC16IS750IPW,112 part is unused and in its original packaging.
Return procedure for SC16IS750IPW,112:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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