NXP Semiconductors SC16IS760IPW,112
- Part No.:
- SC16IS760IPW,112
- Manufacturer:
- NXP Semiconductors
- Category:
- Controllers
- Package:
- 24-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
SC16IS760IPW,112.pdf
- Description:
- IC UART 64BYTE 24TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SC16IS760IPW,112 from NXP Semiconductors is a single-channel high-performance UART with I²C-bus or SPI slave interface, supporting up to 5 Mbit/s data rates, 64-byte TX/RX FIFOs, IrDA SIR up to 1.152 Mbit/s, and 8 programmable GPIOs. It operates at 2.5 V or 3.3 V, features auto hardware/software flow control, automatic RS-485 direction control, and targets embedded industrial serial bridging in space-constrained battery-powered systems.
For engineers reviewing the SC16IS760IPW,112 datasheet, SC16IS760IPW,112 pinout, SC16IS760IPW,112 application, or SC16IS760IPW,112 equivalent, key selection considerations include SPI clock speed (15 Mbit/s), IrDA SIR capability (1.152 Mbit/s), TSSOP24 package compatibility, GPIO configuration flexibility, and register-level backward compatibility with 16C450 UARTs.
Technical Context
The SC16IS760IPW,112 implements a full-duplex UART core with dual-mode serial host interface-selectable via the I2C/SPI pin-and integrates a 16C450-compatible register set for seamless software porting. Its internal architecture includes independent 64-byte transmit and receive FIFOs with programmable trigger levels, an enhanced feature register (EFR) enabling auto RTS/CTS, and dedicated IrDA encoder/decoder logic supporting SIR at 1.152 Mbit/s.
It supports both crystal (XTAL1/XTAL2) and external clock inputs, delivers sleep current <30 µA at 3.3 V, and provides eight bidirectional GPIOs (GPIO0–GPIO7) with configurable modem signal mapping (DSR/DTR/CD/RI). The device operates across −40 °C to +95 °C and is designed for protocol translation between I²C/SPI masters and RS-232/RS-485 physical layers.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Interface | Selectable I²C-bus (400 kbit/s) or SPI (15 Mbit/s max); slave-only operation |
| UART Data Rate | Up to 5 Mbit/s in 16× clock mode; enables high-speed serial bridging without CPU overhead |
| FIFO Depth | 64 bytes each for TX and RX; reduces interrupt frequency and host polling burden |
| IrDA Support | SIR mode up to 1.152 Mbit/s; built-in encoder/decoder eliminates external transceiver need |
| GPIO Pins | 8 programmable I/O pins (GPIO0–GPIO7); configurable as general-purpose or modem signals (DSR/DTR/CD/RI) |
| Supply Voltage | 2.5 V or 3.3 V operation; compatible with modern low-voltage microcontroller I/O domains |
| Temperature Range | −40 °C to +95 °C industrial grade; suitable for factory automation and outdoor edge devices |
Pinout & Package
TSSOP24 package (SOT355-1): plastic thin shrink small outline, 24 leads, 4.4 mm body width, lead pitch 0.65 mm; thermally enhanced for continuous UART operation in compact PCB layouts.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD | Power supply | 2.5 V or 3.3 V main supply; decoupling required per layout guidelines |
| VSS | Ground | Digital ground reference; two dedicated pins for low-noise return path |
| I2C/SPI | Interface select | Logic HIGH = I²C mode; LOW = SPI mode; sets internal bus controller configuration |
| CS/A0 | Chip select / I²C address bit | SPI: active-low chip select (Schmitt-trigger); I²C: LSB of 7-bit slave address |
| SI/A1 | Data input / I²C address bit | SPI: serial data input; I²C: MSB of 7-bit slave address |
| SCL/SCLK | Clock input | I²C: serial clock input; SPI: serial clock input (Mode 0, CPOL=0, CPHA=0) |
| SDA | I²C data I/O | Open-drain I²C-bus data line; must be pulled up externally; undefined in SPI mode |
| SO | SPI data output | 3-stateable SPI serial output; undefined and must be NC in I²C mode |
| IRQ | Interrupt output | Open-drain active-LOW interrupt; requires external pull-up (1 kΩ @ 3.3 V) |
| RESET | Hardware reset | Active-LOW asynchronous reset; initializes registers but preserves DLL/DLH/XON/XOFF values |
| TX | UART transmit output | CMOS-level serial output; disabled during local loopback mode |
| RX | UART receive input | CMOS-level serial input; disabled during local loopback mode |
| RTS | Request to send | Active-LOW UART control output; used for auto RTS flow control or RS-485 driver enable |
| CTS | Clear to send | Active-LOW UART control input; enables auto CTS flow control when EFR[7] is set |
| GPIO0–GPIO3 | Programmable I/O | General-purpose bidirectional pins; default as inputs after reset |
| GPIO4/DSR–GPIO7/RI | Modem signal I/O | Configurable as DSR/DTR/CD/RI per IOControl register; supports legacy modem handshaking |
| XTAL1/XTAL2 | Clock source | Crystal oscillator inputs (1–24 MHz typical); supports external clock injection at XTAL1 |
Key Features
| Feature | Design Value |
|---|---|
| Auto hardware flow control | Independent RTS/CTS activation via EFR[6:7]; prevents RX FIFO overrun without host intervention |
| Software flow control | Programmable Xon/Xoff characters (single/dual) with configurable detection logic; reduces host polling load |
| RS-485 driver control | RTS pin directly controls RS-485 transceiver direction; optional polarity inversion via register bit |
| 16C450 register compatibility | Full backward software compatibility; enables drop-in replacement and rapid firmware porting |
| Low-power sleep mode | Typical sleep current <30 µA at 3.3 V; ideal for battery-operated portable and IoT edge nodes |
| Internal loopback mode | Self-test capability routing TX to RX internally; validates UART functionality without external wiring |
Applications
| Industrial Serial Gateway | Portable Diagnostic Tool |
|---|---|
Use Scenario: Integrating legacy RS-485 fieldbus sensors into an I²C-based PLC controller. IC Role / Device Role / Timing Role: Protocol bridge converting I²C commands from host MCU to RS-485 UART frames; manages RTS-driven transceiver direction and auto CTS handshake. Use Value: Eliminates need for discrete level shifters and external flow control logic; 64-byte FIFO sustains burst traffic from multi-sensor networks. |
Use Scenario: Handheld medical device tester communicating with embedded diagnostic ports over RS-232. IC Role / Device Role / Timing Role: SPI-to-UART bridge enabling low-pin-count MCU to drive full-duplex serial diagnostics; IrDA SIR supports wireless configuration sync. Use Value: Reduces BOM count by integrating UART, GPIOs, and IrDA PHY; 3.3 V operation extends battery life in AA/AAA-powered tools. |
| Factory Automation Node | Smart Energy Meter Interface |
Use Scenario: Adding isolated RS-485 telemetry to a microcontroller-based motor controller board. IC Role / Device Role / Timing Role: UART peripheral with GPIOs repurposed as DTR/DSR for modem-style command acknowledgment; automatic RTS toggling synchronizes with transceiver enable timing. Use Value: Enables deterministic RS-485 half-duplex timing without software delay loops; industrial temperature range ensures reliability near motors and drives. |
Use Scenario: AMI meter using SPI master MCU to communicate with metrology ICs and external HAN modems via RS-232. IC Role / Device Role / Timing Role: Dual-role interface: SPI slave for MCU control, UART transmitter/receiver for metrology data logging and remote firmware updates. Use Value: 64-byte FIFO buffers burst reads from ADCs; software reset allows safe reconfiguration without power cycling the entire meter. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar UART bridge applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SC16IS750IPW | Max SPI clock 4 Mbit/s; IrDA SIR limited to 115.2 kbit/s; identical pinout and register map | Lower-cost option where high-speed SPI or 1.152 Mbit/s IrDA is unnecessary | Select SC16IS750IPW if system SPI clock ≤4 Mbit/s and IrDA SIR speed ≤115.2 kbit/s suffices |
| MAX3107ETJ+ | 3.3 V only; SPI-only interface; no I²C support; 128-byte FIFO; integrated crystal oscillator | Better suited for SPI-centric designs requiring larger FIFO or on-chip clock generation | Choose MAX3107ETJ+ when I²C interface is not needed and higher FIFO depth or integrated clock simplifies layout |
Compared with SC16IS750IPW, SC16IS760IPW,112 adds 15 Mbit/s SPI and 1.152 Mbit/s IrDA SIR-critical for high-throughput or wireless-configured edge nodes-while maintaining identical GPIO, interrupt, and register behavior. Against MAX3107ETJ+, it trades SPI-only simplicity for dual-interface flexibility and lower IrDA latency, at the cost of external clock dependency.
Availability
SC16IS760IPW,112 is available at Aetrix Electronics and suitable for industrial serial gateways, portable diagnostic tools, factory automation nodes, and smart energy meter interfaces requiring stable component supply and long-term manufacturability.
Supply support for SC16IS760IPW,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT applications, with deep expertise in mixed-signal and interface IP.
The SC16IS760IPW,112 belongs to NXP's SC16IS7xx UART bridge family, engineered specifically for low-power, space-constrained embedded systems needing robust I²C/SPI-to-serial protocol conversion with industrial-grade reliability.
FAQ
What communication interfaces does the SC16IS760IPW,112 support?
The SC16IS760IPW,112 supports two selectable slave interfaces: I²C-bus (up to 400 kbit/s) and SPI (up to 15 Mbit/s), configured via the I2C/SPI pin. It does not support master-mode operation. Both interfaces access the same UART register set and GPIO control registers, enabling flexible host processor integration without redesigning firmware for either bus type. The SC16IS760IPW,112 maintains full register compatibility across modes.
Does the SC16IS760IPW,112 support automatic RS-485 direction control?
Yes, the SC16IS760IPW,112 supports automatic RS-485 driver direction control using the RTS pin. When enabled via the Enhanced Feature Register (EFR), RTS asserts before transmission and deasserts after the final stop bit, eliminating external direction-control logic. Polarity inversion is configurable, and the feature works identically in both I²C and SPI modes. This capability is confirmed in the official NXP datasheet Rev. 7 section 2.1.
How many GPIO pins does the SC16IS760IPW,112 provide, and what are their functions?
The SC16IS760IPW,112 provides eight bidirectional GPIO pins (GPIO0–GPIO7). GPIO0–GPIO3 operate exclusively as general-purpose I/O. GPIO4–GPIO7 can be configured either as GPIOs or as modem control signals (DSR, DTR, CD, RI) via the IOControl register. All eight pins retain their state through software reset and support interrupt-on-change functionality, making them suitable for status monitoring or auxiliary control in compact embedded designs.
What is the maximum IrDA SIR speed supported by the SC16IS760IPW,112?
The SC16IS760IPW,112 supports IrDA SIR (Serial Infrared) at up to 1.152 Mbit/s, distinguishing it from the SC16IS750IPW (limited to 115.2 kbit/s). This higher speed enables faster wireless configuration and firmware updates in portable tools and handheld devices. The built-in encoder/decoder handles all IrDA framing, requiring no external components. Note that 1.152 Mbit/s SIR is not compatible with IrDA MIR at the same rate.
Is the SC16IS760IPW,112 pin-compatible with other devices in the SC16IS7xx family?
Yes, the SC16IS760IPW,112 is pin-compatible with the SC16IS750IPW in the TSSOP24 package (SOT355-1), sharing identical pinout, footprint, and voltage ratings. It is not pin-compatible with the SC16IS740IPW (TSSOP16) or HVQFN24 variants due to differing lead counts and layouts. This allows direct substitution in existing SC16IS750IPW designs when upgrading to 15 Mbit/s SPI or 1.152 Mbit/s IrDA SIR capability.
SC16IS760IPW,112 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 24-TSSOP (0.173", 4.40mm Width)
- Programmable:
- Not Verified
- Protocol:
- RS232, RS485
- Function:
- Controller
- Interface:
- I2C, SPI, UART
- Standards:
- -
- Voltage - Supply:
- 2.5V, 3.3V
- Current - Supply:
- 6mA
- Operating Temperature:
- -40°C ~ 95°C
- Supplier Device Package:
- 24-TSSOP
- Grade:
- -
- Qualification:
- -
SC16IS760IPW,112 FAQ
1.How can I place an order for SC16IS760IPW,112 through Aetrix?
Please submit a Request for Quotation (RFQ) for SC16IS760IPW,112 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SC16IS760IPW,112 reliable?
The price and inventory of SC16IS760IPW,112 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SC16IS760IPW,112 is usually 5 days.
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6.How does Aetrix verify that SC16IS760IPW,112 is sourced from the original manufacturer or authorized distributors?
All SC16IS760IPW,112 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SC16IS760IPW,112 meets industry standards.
7.What is the process for return or replacement of SC16IS760IPW,112?
All SC16IS760IPW,112 units undergo pre-shipment inspection (PSI). If there is an issue with SC16IS760IPW,112, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SC16IS760IPW,112 part is unused and in its original packaging.
Return procedure for SC16IS760IPW,112:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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