NXP Semiconductors SC16IS850LIPW,118
- Part No.:
- SC16IS850LIPW,118
- Manufacturer:
- NXP Semiconductors
- Package:
- 24-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
SC16IS850LIPW,118.pdf
- Description:
- IC UART I2C/SPI 24TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SC16IS850LIPW,118 from NXP Semiconductors is a single-channel UART IC with dual I²C-bus or SPI slave interface, 128-byte TX/RX FIFOs, IrDA SIR support up to 115.2 kbit/s, and RS-485 automatic direction control via RTS. It operates at 1.8 V, supports baud rates up to 5 Mbit/s (with 80 MHz clock), and targets low-power industrial serial bridging in battery-operated handheld devices.
For engineers reviewing the SC16IS850LIPW,118 datasheet, SC16IS850LIPW,118 pinout, SC16IS850LIPW,118 application, or SC16IS850LIPW,118 equivalent, key selection criteria include I²C/SPI interface select logic, TSSOP24 package compatibility, 128-byte FIFO programmability, auto RS-485 driver control timing, and 1.8 V sleep current < 5 µA.
Technical Context
The SC16IS850LIPW,118 implements a fully programmable UART core with backward-compatible 16C450 register mapping, supporting both 32-byte and extended 128-byte FIFO modes controlled by TXINTLVL/RXINTLVL registers. Its baud rate generator uses rational division (DLL/DLM + CLKPRES) for precise custom rates up to 5 Mbit/s.
Hardware flow control is implemented via RTS/CTS with EFR[6:7] enable, while software flow control uses configurable Xon/Xoff characters (Xon1/Xon2/Xoff1/Xoff2). RS-485 direction control is managed automatically through RTS assertion/deassertion with optional inversion via AFCR1[1], and IrDA encoding/decoding is integrated on-die.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Interface Type | I²C-bus (Fast-mode, 400 kbit/s) or SPI (Mode 0, 12 Mbit/s); slave-only; selected by I2C/SPI pin logic level |
| UART Data Rate | Up to 5 Mbit/s (16× clock mode with 80 MHz XTAL1 input); 1.5 Mbit/s with crystal oscillator |
| FIFO Depth | 128 bytes each for transmit and receive; programmable trigger levels (1–128) in extended mode |
| Supply Voltage | 1.8 V nominal; enables ultra-low-power operation with sleep current < 5 µA |
| Operating Temp | −40 °C to +85 °C; qualified for industrial environments |
| IrDA Support | Built-in encoder/decoder for SIR physical layer at up to 115.2 kbit/s |
| RS-485 Control | Automatic driver direction control via RTS signal; configurable polarity inversion |
Pinout & Package
SC16IS850LIPW,118 is housed in a plastic thin shrink small outline package (TSSOP24) with 24 leads, body width 4.4 mm (SOT355-1), lead pitch 0.65 mm, and exposed pad not present - suitable for standard reflow assembly.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| RX (Pin 1) | UART receiver input | Asynchronous serial data input; disabled during local loopback mode |
| TX (Pin 2) | UART transmitter output | Asynchronous serial data output; internally disconnected in loopback mode |
| I2C/SPI (Pin 23) | Interface select | Logic HIGH = I²C mode; LOW = SPI mode; internal pull-up allows unconnected default to I²C |
| CS/A0 (Pin 11) | SPI chip select / I²C address bit A0 | Active LOW SPI CS; or LSB of 7-bit I²C slave address when I2C/SPI = HIGH |
| SI/A1 (Pin 10) | SPI data input / I²C address bit A1 | Serial data input for SPI; or MSB of I²C address when I2C/SPI = HIGH |
| SCL/SCLK (Pin 24) | I²C clock / SPI clock | Input for both interfaces; requires external pull-up for I²C; Schmitt-triggered for SPI |
| SDA (Pin 21) | I²C bidirectional data | Open-drain I²C data line; must be tied to VSS if SPI mode selected |
| IRQ (Pin 12) | Interrupt output | Open-drain, active LOW; signals RX/TX FIFO status, modem events, or errors |
| RTS (Pin 13) | Request-to-send output | Active LOW; controls RS-485 driver direction; polarity invertible via AFCR1[1] |
| CTS (Pin 16) | Clear-to-send input | Active LOW; enables hardware flow control when EFR[7] = 1 |
| RESET (Pin 15) | Hardware reset input | Active LOW asynchronous reset; initializes registers to 16C550B-compatible state |
| XTAL1 (Pin 4) | Clock input | Crystal or external clock source (up to 80 MHz); DC blocking cap required if >50 MHz |
| XTAL2 (Pin 5) | Clock output | Crystal oscillator output; left unconnected in external clock mode |
| VDD (Pin 20) | Power supply | 1.8 V ±10 %; decoupling capacitor required per datasheet layout guidelines |
| VSS (Pin 6) | Ground | Reference for all digital and analog circuitry; must be low-impedance connection |
Key Features
| Feature | Design Value |
|---|---|
| Auto RS-485 direction control | Eliminates external transceiver control logic by using RTS to toggle driver enable with programmable turn-around delay (RS485TIME register) |
| 128-byte programmable FIFO | Reduces CPU interrupt load by enabling burst reads/writes; trigger levels set independently per channel (1–128 bytes) |
| Software reset capability | Allows full UART reinitialization without external hardware reset signal, preserving system-level power sequencing |
| Backward register compatibility | Enables drop-in replacement of legacy 16C450/16C650 firmware with minimal driver modification |
| IrDA SIR physical layer integration | Removes need for discrete IrDA encoder/decoder ICs; supports standard 115.2 kbit/s infrared communication |
Applications
| Industrial Serial Gateway | Portable Diagnostic Tool |
|---|---|
Use Scenario: Connecting legacy RS-232/RS-485 field instruments to an I²C-based PLC controller in factory automation. IC Role / Device Role / Timing Role: UART bridge translating between I²C master and asynchronous serial peripherals; manages protocol conversion, flow control, and RS-485 bus arbitration. Use Value: Enables seamless integration without FPGA or microcontroller firmware changes; 128-byte FIFO prevents data loss during high-speed sensor bursts. | Use Scenario: Handheld medical device communicating with Bluetooth-enabled PC via RS-232 TTL-level interface. IC Role / Device Role / Timing Role: Low-voltage UART interface providing IrDA SIR and hardware flow control between MCU and modem IC. Use Value: 1.8 V operation and <5 µA sleep current extend battery life; auto RTS/CTS eliminates software polling overhead. |
| Smart Energy Meter Interface | Modem-Controlled Remote Terminal Unit |
Use Scenario: Adding secure, isolated serial communication to a three-phase electricity meter using RS-485 for AMI backhaul. IC Role / Device Role / Timing Role: RS-485 transceiver companion IC handling direction control, framing, and error detection for HART or DLMS protocols. Use Value: Automatic RS-485 driver control ensures reliable half-duplex timing; 128-byte FIFO accommodates large DLMS read responses without overflow. | Use Scenario: Cellular-connected RTU collecting data from multiple sensors and forwarding via AT command interface over UART. IC Role / Device Role / Timing Role: Primary UART interface managing modem handshaking (DTR/DSR/CD/RI), software flow control (Xon/Xoff), and interrupt-driven buffer management. Use Value: Programmable Xon/Xoff characters prevent command corruption during cellular network latency spikes; IRQ pin enables efficient event-driven polling. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar UART bridge applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SC16IS750IPW | 64-byte FIFO (vs. 128-byte), no IrDA SIR, same TSSOP24 package and I²C/SPI interface | Limited buffer depth reduces suitability for high-throughput or bursty protocols like DLMS or Modbus TCP tunneling | Select when cost sensitivity outweighs FIFO depth requirement and IrDA is unused |
| MAX3107EAE+T | 3.3 V only, SPI-only interface, 128-byte FIFO, no RS-485 auto-control or IrDA | Requires external level-shifting for 1.8 V systems; lacks integrated RS-485 direction logic and infrared PHY | Choose for 3.3 V designs where SPI simplicity and MAXIM's robust ESD rating are prioritized |
Compared with SC16IS750IPW, the SC16IS850LIPW,118 delivers double FIFO depth and IrDA SIR-critical for energy metering and portable diagnostics-while MAX3107EAE+T trades voltage flexibility and RS-485 integration for higher ESD tolerance and SPI-only simplicity in 3.3 V infrastructure.
Availability
SC16IS850LIPW,118 is available at Aetrix Electronics and suitable for factory automation gateways, portable diagnostic tools, and smart energy meter interfaces requiring stable component supply, long-term industrial lifecycle support, and guaranteed 1.8 V operation.
Supply support for SC16IS850LIPW,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT applications.
The SC16IS850LIPW,118 belongs to NXP's SC16IS family of intelligent UART bridges, designed specifically to simplify serial protocol translation in resource-constrained, low-voltage embedded systems with stringent power and space requirements.
FAQ
What interface modes does the SC16IS850LIPW,118 support?
The SC16IS850LIPW,118 supports two mutually exclusive slave interface modes: I²C-bus (Fast-mode, up to 400 kbit/s) and SPI (Mode 0, up to 12 Mbit/s), selected by the logic level on the I2C/SPI pin. In I²C mode, it uses a 7-bit slave address configurable via A0/A1 pins; in SPI mode, it responds to chip-select assertion and uses SI/SO lines for data transfer. Both interfaces access the same internal UART register set.
How does the SC16IS850LIPW,118 implement automatic RS-485 direction control?
The SC16IS850LIPW,118 uses its RTS output pin to drive the DE/RE control inputs of an external RS-485 transceiver. When automatic RS-485 mode is enabled (via AFCR1[0]), the device asserts RTS before transmitting and deasserts it after transmission completes, with a programmable turn-around delay set in the RS485TIME register. Polarity inversion is supported via AFCR1[1], allowing direct compatibility with both active-HIGH and active-LOW transceiver enable logic.
What is the maximum UART baud rate achievable with the SC16IS850LIPW,118?
The SC16IS850LIPW,118 supports UART data rates up to 5 Mbit/s when driven by an 80 MHz clock applied to the XTAL1 pin in 16× oversampling mode. With a crystal oscillator (e.g., 1.8432 MHz), the maximum achievable rate is 1.5 Mbit/s. Baud rate accuracy is enhanced by the rational divisor architecture (DLL/DLM + CLKPRES), enabling precise custom rates such as 921.6 kbit/s or 2.5 Mbit/s without external clock trimming.
Does the SC16IS850LIPW,118 support hardware flow control, and how is it configured?
Yes, the SC16IS850LIPW,118 supports auto hardware flow control using RTS/CTS signals. It is enabled by setting EFR[6] (RTS control) and EFR[7] (CTS monitoring) to 1. When CTS goes LOW, transmission halts after the current character's stop bit; resumption occurs when CTS returns HIGH. The RTS pin can also be mapped to DTR and CTS to DSR via AFCR1[2], allowing reuse of modem control pins in compact designs.
What is the function of the 128-byte FIFO in the SC16IS850LIPW,118, and how is it programmed?
The 128-byte FIFO in the SC16IS850LIPW,118 reduces host processor interrupt frequency by buffering up to 128 bytes of received or transmitted data. It is activated by writing non-zero values to TXINTLVL or RXINTLVL registers (first extra feature register set), which then define programmable trigger levels (1–128 bytes). Unlike legacy 32-byte mode, this extended mode eliminates FIFO underflow/overflow in high-throughput applications like DLMS meter reading or firmware updates over serial.
SC16IS850LIPW,118 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 24-TSSOP (0.173", 4.40mm Width)
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Features:
- -
- Number of Channels:
- 1, UART
- FIFO's:
- 128 Byte
- Protocol:
- RS232, RS485
- Data Rate (Max):
- 5Mbps
- Voltage - Supply:
- 1.65V ~ 1.95V
- With Auto Flow Control:
- Yes
- With IrDA Encoder/Decoder:
- Yes
- With False Start Bit Detection:
- Yes
- With Modem Control:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-TSSOP
SC16IS850LIPW,118 FAQ
1.How can I place an order for SC16IS850LIPW,118 through Aetrix?
Please submit a Request for Quotation (RFQ) for SC16IS850LIPW,118 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SC16IS850LIPW,118 reliable?
The price and inventory of SC16IS850LIPW,118 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SC16IS850LIPW,118 is usually 5 days.
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Once your SC16IS850LIPW,118 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SC16IS850LIPW,118?
For technical support, including SC16IS850LIPW,118 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SC16IS850LIPW,118 requirements.
6.How does Aetrix verify that SC16IS850LIPW,118 is sourced from the original manufacturer or authorized distributors?
All SC16IS850LIPW,118 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SC16IS850LIPW,118 meets industry standards.
7.What is the process for return or replacement of SC16IS850LIPW,118?
All SC16IS850LIPW,118 units undergo pre-shipment inspection (PSI). If there is an issue with SC16IS850LIPW,118, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SC16IS850LIPW,118 part is unused and in its original packaging.
Return procedure for SC16IS850LIPW,118:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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