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Home > Products > Integrated Circuits (ICs) > Interface > Controllers

NXP Semiconductors SC18IS602IPW,128

Name: SC18IS602IPW,128
Brand: NXP Semiconductors
SKU: SC18IS602IPW,128
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SC18IS602IPW,128

Manufacturer:: NXP Semiconductors

Category:: Controllers

Package:: 16-TSSOP (0.173", 4.40mm Width)

Datasheet:: SC18IS602IPW,128.pdf

Description:: IC BRIDGE SPI/I2C 16-TSSOP

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Product details

Overview

SC18IS602IPW,128 from NXP Semiconductors is an I²C-to-SPI bridge IC operating as an I²C-bus slave and SPI master, enabling microcontrollers with only I²C interfaces to communicate with SPI peripherals. It features a 200-byte data buffer, internal oscillator (7.3728 MHz ±1%), 400 kHz I²C interface, and 1.8 Mbit/s SPI master capability. It is used in embedded systems requiring protocol translation between legacy I²C hosts and SPI flash, EEPROMs, or sensors.

For engineers reviewing the SC18IS602IPW,128 datasheet, SC18IS602IPW,128 pinout, SC18IS602IPW,128 application, or SC18IS602IPW,128 equivalent, key selection criteria include its fixed internal oscillator (no external clock required), SS2 pin disabled (GPIO2-only function), TSSOP16 package compatibility, and support for up to four SPI slave select outputs via programmable GPIO mapping.

Technical Context

The SC18IS602IPW,128 implements a dedicated hardware bridge architecture: its I²C interface operates strictly as a slave (no master capability), while its SPI interface functions exclusively as a master with full Mode 0–3 support and configurable clock polarity/phase. The device uses a synchronous internal RC oscillator-trimmed to ±1% at 25 °C-eliminating need for external timing components.

All SPI transactions are initiated and controlled via I²C commands: Function IDs (01h–0Fh) trigger SPI transfers using selected SSn lines; F0h configures SPI mode/frequency; F4h/F5h/F6h/F7h manage GPIO state, readback, enable, and per-pin configuration (quasi-bidirectional, push-pull, open-drain, or input-only). Interrupt signaling (active LOW INT) indicates SPI transaction completion.

Key Specifications

Parameter	Value and Actual Design Meaning
I²C Interface Speed	Up to 400 kHz - supports Fast-mode I²C, enabling high-throughput command/data transfer from host MCU without bus arbitration overhead.
SPI Master Speed	Up to 1.8 Mbit/s - derived from internal 7.3728 MHz oscillator (f_osc/4), sufficient for SPI EEPROM, flash, and sensor interfacing.
Data Buffer Depth	200 bytes - accommodates multi-byte SPI reads/writes (e.g., 256-bit AES keys or 128-byte sensor bursts) without host intervention.
Supply Voltage Range	2.4 V to 3.6 V - compatible with 3.3 V logic systems; supports operation across industrial temperature range (−40 °C to +85 °C).
Interrupt Output	Active LOW INT pin - signals SPI transaction completion; cleared via F1h command or automatically on next I²C address match.
GPIO Capability	Up to 4 programmable I/O pins (SS0–SS3) - configurable as slave selects or GPIO with software-defined electrical types (quasi-bidirectional, push-pull, etc.).
ESD Protection	2000 V HBM (JESD22-A114), 200 V MM (JESD22-A115), 1000 V CDM (JESD22-C101) - ensures robustness in handling and board-level integration.

Pinout & Package

SC18IS602IPW,128 is housed in a 16-pin TSSOP package (SOT403-1), 4.4 mm body width, lead pitch 0.65 mm, RoHS-compliant. Pinout validated per NXP datasheet Rev. 04 (2008), Figure 3a and Table 2.

Pin/Terminal	Circuit Role	Design Meaning
1: SS0/GPIO0	I/O	SPI slave select output 0 (active LOW) or general-purpose I/O; default function is SS0; reconfigurable as GPIO via F6h/F7h.
2: SS1/GPIO1	I/O	SPI slave select output 1 (active LOW) or general-purpose I/O; supports concurrent multi-device SPI addressing.
3: RESET	Input	Active LOW reset input; includes internal 10–30 kΩ pull-up; resets address latch and internal state on assertion.
4: VSS	Power	Ground reference for all digital and analog circuitry; requires low-impedance connection to system GND plane.
5: MISO	Input	Master In, Slave Out - receives serial data from SPI slave devices during read operations; sampled on SPICLK edge per configured mode.
6: MOSI	Output	Master Out, Slave In - transmits serial data to SPI slave devices; driven synchronously with SPICLK.
7: SDA	I/O	I²C-bus data line - bidirectional, open-drain; requires external pull-up resistor (typically 2.2–4.7 kΩ to VDD).
8: SCL	Input	I²C-bus clock line - driven by I²C master; SC18IS602IPW,128 holds SCL LOW between bytes if internal processing is incomplete.
9: INT	Output	Interrupt output (active LOW) - asserts after SPI transaction completion; cleared by F1h command or automatic I²C address detection.
10: SS2/GPIO2	I/O	GPIO2 only - SC18IS602IPW,128 does not support SS2 function; must be used exclusively as general-purpose I/O.
11: SPICLK	Output	SPI clock output - generated internally; frequency set via F0h command (1843/461/115/58 kHz options); drives all connected SPI slaves.
12: VDD	Power	Supply voltage input (2.4–3.6 V); bypass capacitor (100 nF ceramic) required near pin for noise suppression.
13: SS3/GPIO3	I/O	SPI slave select output 3 (active LOW) or general-purpose I/O; usable as fourth independent SS line or GPIO.
14: A0	Input	I²C slave address bit 0 - latched at RESET; enables up to 8 devices on same I²C bus (A2/A1/A0 combination).
15: A1	Input	I²C slave address bit 1 - latched at RESET; determines unique 7-bit I²C address (base 0x50 + A2:A1:A0).
16: A2	Input	I²C slave address bit 2 - latched at RESET; completes 3-bit programmable address field for multi-drop I²C configuration.

Key Features

Feature	Design Value
Internal RC Oscillator	7.3728 MHz ±1% (25 °C) - eliminates external crystal/clock source, reducing BOM count and PCB footprint for cost-sensitive designs.
Four Configurable SS Outputs	SS0–SS3 can be independently assigned as SPI slave selects or GPIOs - enables direct control of up to four SPI peripherals without external logic.
Per-Pin GPIO Configuration	Each GPIO supports quasi-bidirectional, push-pull, open-drain, or input-only modes via F7h register - allows precise drive strength and signal integrity tuning.
200-Byte FIFO Buffer	Decouples I²C and SPI timing domains - permits burst I²C writes followed by autonomous SPI execution, freeing host MCU resources.
Low-Power Idle Mode	F2h command reduces supply current to ≤3.9 mA (VDD = 3.6 V) - extends battery life in portable or energy-constrained applications.

Applications

Industrial Sensor Hub	Legacy MCU SPI Expansion
Use Scenario: A Cortex-M0+ microcontroller with I²C-only peripheral interface must read data from four SPI-based environmental sensors (temperature, humidity, pressure, gas). IC Role / Device Role / Timing Role: SC18IS602IPW,128 acts as protocol translator and SPI master controller, managing time-critical SPI timing while presenting a simple byte-oriented I²C register map to the host. Use Value: Enables use of low-cost I²C-only MCU without redesigning PCB or adding external level shifters or clock generators.	Use Scenario: An older 8-bit microcontroller lacks native SPI hardware but must program external SPI flash memory for firmware updates. IC Role / Device Role / Timing Role: SC18IS602IPW,128 serves as off-chip SPI master, executing flash write/erase sequences with precise t_W, t_PP, and t_SE timing compliance. Use Value: Eliminates need for MCU firmware rewrite or hardware upgrade; supports standard SPI flash command sets (e.g., W25Q80DV) via I²C command packets.
Modular I/O Expansion	Secure Element Interface
Use Scenario: A PLC base unit uses I²C to configure and monitor multiple remote I/O modules, each containing SPI DACs, ADCs, and GPIO expanders. IC Role / Device Role / Timing Role: SC18IS602IPW,128 provides isolated SPI bus segments per module, with SS0–SS3 enabling independent chip-select control and preventing bus contention. Use Value: Simplifies system-level I²C topology while maintaining deterministic SPI timing across distributed nodes.	Use Scenario: A payment terminal integrates an I²C-connected secure element (e.g., ATECC608A) alongside SPI-based cryptographic co-processors for key derivation and signing. IC Role / Device Role / Timing Role: SC18IS602IPW,128 bridges host processor's I²C bus to SPI crypto IC, handling encrypted command framing and response buffering. Use Value: Maintains separation of security domains while leveraging existing I²C infrastructure for secure boot and attestation workflows.

Industrial Sensor Hub

Legacy MCU SPI Expansion

Use Scenario: A Cortex-M0+ microcontroller with I²C-only peripheral interface must read data from four SPI-based environmental sensors (temperature, humidity, pressure, gas).

IC Role / Device Role / Timing Role: SC18IS602IPW,128 acts as protocol translator and SPI master controller, managing time-critical SPI timing while presenting a simple byte-oriented I²C register map to the host.

Use Value: Enables use of low-cost I²C-only MCU without redesigning PCB or adding external level shifters or clock generators.

Use Scenario: An older 8-bit microcontroller lacks native SPI hardware but must program external SPI flash memory for firmware updates.

IC Role / Device Role / Timing Role: SC18IS602IPW,128 serves as off-chip SPI master, executing flash write/erase sequences with precise t_W, t_PP, and t_SE timing compliance.

Use Value: Eliminates need for MCU firmware rewrite or hardware upgrade; supports standard SPI flash command sets (e.g., W25Q80DV) via I²C command packets.

Modular I/O Expansion

Secure Element Interface

Use Scenario: A PLC base unit uses I²C to configure and monitor multiple remote I/O modules, each containing SPI DACs, ADCs, and GPIO expanders.

IC Role / Device Role / Timing Role: SC18IS602IPW,128 provides isolated SPI bus segments per module, with SS0–SS3 enabling independent chip-select control and preventing bus contention.

Use Value: Simplifies system-level I²C topology while maintaining deterministic SPI timing across distributed nodes.

Use Scenario: A payment terminal integrates an I²C-connected secure element (e.g., ATECC608A) alongside SPI-based cryptographic co-processors for key derivation and signing.

IC Role / Device Role / Timing Role: SC18IS602IPW,128 bridges host processor's I²C bus to SPI crypto IC, handling encrypted command framing and response buffering.

Use Value: Maintains separation of security domains while leveraging existing I²C infrastructure for secure boot and attestation workflows.

Equivalent & Alternatives

The following parts are listed as comparable options for similar I²C-to-SPI bridge applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SC18IS602BIPW	Supports SS2 as functional slave select (not GPIO-only); identical pinout, oscillator, and I²C/SPI specs.	Required when dual SS2-controlled SPI peripherals are needed; SC18IS602IPW,128 cannot assert SS2 as active LOW.	Select SC18IS602BIPW only if SS2 functionality is mandatory; otherwise SC18IS602IPW,128 offers same core bridging with lower cost and simpler GPIO assignment.
SC18IS603IPW	Requires external 0–18 MHz clock on CLKIN; supports higher 4 Mbit/s SPI speed; no internal oscillator.	Suitable for systems with existing clock distribution; not drop-in replaceable due to missing internal oscillator and CLKIN pin instead of SS2/GPIO2.	Choose SC18IS603IPW only when >1.8 Mbit/s SPI throughput is required and external clock is available; SC18IS602IPW,128 is preferred for self-contained, low-component-count designs.

Compared with SC18IS602BIPW and SC18IS603IPW, the SC18IS602IPW,128 trades SS2 functionality and maximum SPI speed for guaranteed oscillator autonomy and simplified power-up sequencing-making it optimal for space-constrained, cost-sensitive I²C-hosted SPI peripheral integration where <1.8 Mbit/s suffices.

Availability

SC18IS602IPW,128 is available at Aetrix Electronics and suitable for industrial sensor hubs, legacy MCU SPI expansion, modular I/O systems, and secure element interfaces requiring stable component supply and long-term manufacturability.

Supply support for SC18IS602IPW,128 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT applications, with deep expertise in interface, power, and security ICs.

The SC18IS602IPW,128 belongs to NXP's I²C-to-SPI bridge product line, designed specifically to extend legacy microcontroller capabilities into SPI-based peripheral ecosystems without requiring FPGA or custom ASIC development.

FAQ

What is the maximum SPI clock frequency supported by SC18IS602IPW,128?

The SC18IS602IPW,128 supports a maximum SPI clock frequency of 1.8 Mbit/s, derived from its internal 7.3728 MHz oscillator divided by 4 (f_osc/4). This is fixed for the SC18IS602 variant; higher speeds require SC18IS603IPW with external clock. The SC18IS602IPW,128 does not support 4 Mbit/s operation.

Can SC18IS602IPW,128 use pin 10 (SS2/GPIO2) as a functional SPI slave select?

No. Per NXP datasheet Rev. 04 Section 6.1 and footnote [1], SC18IS602IPW,128 does not support SS2 functionality on pin 10; that pin is designated GPIO2 only. Attempting to use it as SS2 will not generate a valid slave select signal. Only SC18IS602BIPW supports SS2 on this pin.

How many I²C slave addresses can be configured for SC18IS602IPW,128?

The SC18IS602IPW,128 supports eight unique I²C slave addresses via three hardware-programmable address pins (A2, A1, A0), yielding combinations from 0x50 to 0x57. Address bits are latched at RESET and remain static until next reset; dynamic reconfiguration is not supported.

Does SC18IS602IPW,128 require external pull-up resistors on I²C lines?

Yes. The SDA and SCL pins of SC18IS602IPW,128 are open-drain and require external pull-up resistors to VDD (typically 2.2–4.7 kΩ). No internal pull-ups are enabled by default; omission will prevent I²C communication. Pull-ups must be placed close to the SC18IS602IPW,128 pins for signal integrity.

What GPIO configurations are supported on SC18IS602IPW,128 pins SS0–SS3?

The SC18IS602IPW,128 supports four GPIO modes per pin (SS0–SS3): quasi-bidirectional (default), push-pull, open-drain, and input-only. Configuration is performed via the F7h command and corresponding GPIO Configuration register bits. Each mode affects drive strength, current sourcing/sinking, and input hysteresis behavior.

SC18IS602IPW,128 Specifications

Product attributes: Attribute value

Manufacturer:: NXP Semiconductors

Package/Case:: 16-TSSOP (0.173", 4.40mm Width)

Programmable:: Not Verified

Protocol:: I2C

Function:: Controller

Interface:: SPI

Standards:: -

Voltage - Supply:: 2.4V ~ 3.6V

Current - Supply:: 11mA

Operating Temperature:: -40°C ~ 85°C

Supplier Device Package:: 16-TSSOP

Grade:: -

Qualification:: -

SC18IS602IPW,128 FAQ

1.How can I place an order for SC18IS602IPW,128 through Aetrix?

Please submit a Request for Quotation (RFQ) for SC18IS602IPW,128 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SC18IS602IPW,128 reliable?

The price and inventory of SC18IS602IPW,128 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SC18IS602IPW,128 is usually 5 days.

3.What payment methods are accepted for SC18IS602IPW,128?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SC18IS602IPW,128 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SC18IS602IPW,128?

SC18IS602IPW,128 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SC18IS602IPW,128 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SC18IS602IPW,128?

For technical support, including SC18IS602IPW,128 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SC18IS602IPW,128 requirements.

6.How does Aetrix verify that SC18IS602IPW,128 is sourced from the original manufacturer or authorized distributors?

All SC18IS602IPW,128 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SC18IS602IPW,128 meets industry standards.

7.What is the process for return or replacement of SC18IS602IPW,128?

All SC18IS602IPW,128 units undergo pre-shipment inspection (PSI). If there is an issue with SC18IS602IPW,128, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SC18IS602IPW,128 part is unused and in its original packaging.

Return procedure for SC18IS602IPW,128:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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