NXP Semiconductors SC18IS604PWJ

Overview

SC18IS604PWJ from NXP Semiconductors is a SPI-to-I²C bus bridge IC that enables an SPI master (e.g., microcontroller) to communicate with I²C target devices. It operates as an I²C-bus controller-transmitter/receiver, supports SPI Mode 3 up to 1.2 MHz, delivers Fast-mode I²C at 375 kHz, features 255-byte transmit and receive buffers, and functions across 1.71 V–3.6 V supply with -40 °C to +105 °C temperature range.

For engineers reviewing the SC18IS604PWJ datasheet, SC18IS604PWJ pinout, SC18IS604PWJ application, or SC18IS604PWJ equivalent, key selection considerations include its TSSOP16 package, 5 GPIOs with programmable push-pull/open-drain/input modes, Deep Power-down mode with CS wake-up, active-low open-drain INT output, and 5 V tolerant I/O pins (except MISO).

Technical Context

The SC18IS604PWJ implements a dedicated hardware I²C-bus controller with full protocol handling-including arbitration, START/STOP generation, clock stretching, and timeout detection-offloading timing-critical tasks from the host MCU. Its internal oscillator eliminates external crystal requirements, and register-mapped control (via SPI commands 0x20/0x21) allows dynamic configuration of I²C clock rate (7.4–375 kHz), timeout threshold, GPIO modes, and I²C address.

It uses a dual-buffer architecture: a 255-byte transmit buffer accepts SPI write commands (0x00, 0x02, 0x03) for I²C writes or read-after-write sequences, while a 255-byte receive buffer stores I²C response data until explicitly read via command 0x06. Status reporting occurs through the 8-bit I2CStat register (0xF0–0xF9), with interrupt assertion on INT pin for transaction completion or error conditions.

Key Specifications

Pinout & Package

SC18IS604PWJ is housed in a 16-pin TSSOP package (SOT403-1), 4.4 mm body width, 0.65 mm pitch, lead-free and RoHS compliant. Pin 1 is located in Quadrant 1 (device rotated 180° vs SC18IS600).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar SPI-to-I²C bridge applications.

Compared with SC18IS602PW, SC18IS604PWJ adds GPIO flexibility, extended temperature support, and ultra-low-power Deep Power-down - critical for industrial and battery-operated designs. Versus PCA9306, SC18IS604PWJ replaces firmware-intensive bit-banging with autonomous hardware-based I²C control, reducing MCU load and improving timing reliability.

Availability

SC18IS604PWJ is available at Aetrix Electronics and suitable for industrial sensor hubs, automotive body control modules, medical wearables, and smart home controllers requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for SC18IS604PWJ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with deep expertise in interface, power management, and embedded processing technologies.

The SC18IS604PWJ belongs to NXP's interface bridge product line, designed specifically to simplify integration between legacy or resource-constrained SPI hosts and standardized I²C peripherals in space- and power-sensitive embedded systems.

FAQ

What is the maximum I²C clock frequency supported by SC18IS604PWJ?

The SC18IS604PWJ supports Fast-mode I²C operation up to 375 kHz, configurable via the I2CClk register (address 0x02). This value is achieved with default register setting 0x19; lower values (e.g., 0x05 = 268 kHz, 0x09 = 208 kHz) allow tuning for bus capacitance or noise immunity. The device does not support standard-mode (100 kHz) or high-speed mode (3.4 MHz) I²C.

How does SC18IS604PWJ enter and exit Deep Power-down mode?

SC18IS604PWJ enters Deep Power-down mode by receiving the exact SPI command sequence: 0x30 (command), 0x5A, then 0xA5 - all sent with CS asserted LOW. To exit, the host must deassert and reassert CS (bring CS HIGH then LOW again). Upon wake-up, the device resumes normal SPI operation with internal registers preserved except for I2CStat, which resets to 0xF0.

Can SC18IS604PWJ operate with a 5 V I²C bus while powered from 3.3 V?

Yes - SC18IS604PWJ features 5 V tolerant I/O pins (SDA, SCL, GPIO0–GPIO3, INT) when VDD is ≥1.71 V. This allows direct connection to 5 V pull-ups on the I²C bus without external level shifters. Note: MISO is 3 V tolerant only and must not exceed VDD + 0.3 V.

What happens to the I²C bus during an arbitration loss detected by SC18IS604PWJ?

When SC18IS604PWJ detects arbitration loss during an I²C transaction, it automatically transmits a repeated START condition once the bus becomes free - unless an I²C-bus timeout occurs first. If timeout triggers, the INT pin asserts LOW and status 0xF8 appears in the I2CStat register, requiring host intervention to clear the condition.

How do I read the firmware version string from SC18IS604PWJ?

To read the version string "SC18IS604 1.0.0", send SPI command 0xFE to load the string into the read buffer, then issue command 0x06 to retrieve it via MISO. The 16-byte response includes ASCII characters followed by a null terminator (0x00); subsequent bytes retain prior buffer contents and must be ignored.