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NXP Semiconductors SC26C562C1A,512
- Part No.:
- SC26C562C1A,512
- Manufacturer:
- NXP Semiconductors
- Category:
- Specialized
- Package:
- 52-LCC (J-Lead)
- Datasheet:
-
SC26C562C1A,512.pdf
- Description:
- IC INTERFACE SPECIALIZED 52PLCC
- Quantity:
- Payment:
- Shipping:
Inventory:1,969
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Product details
Overview
SC26C562C1A,512 from NXP Semiconductors (formerly Philips) is a CMOS dual universal serial communications controller (CDUSCC) providing two independent, multi-protocol, full-duplex UART/USART channels in a single PLCC52 package. It supports synchronous (HDLC/SDLC/X.25/BISYNC) and asynchronous modes up to 10 Mbit/s, features 16-deep FIFOs per channel, integrated DPLL, and programmable bit-rate generation from BRG, DPLL, counter/timer, or external clock.
For engineers reviewing the SC26C562C1A,512 datasheet, SC26C562C1A,512 pinout, SC26C562C1A,512 application, or SC26C562C1A,512 equivalent, this device serves as a legacy industrial-grade dual-channel serial controller for embedded telecom, protocol-conversion, and legacy system interface designs requiring hardware-compatible replacement of SCN26562.
Technical Context
The SC26C562C1A,512 implements two fully independent serial channels sharing a common 19-rate bit-rate generator (BRG) and on-chip oscillator, with each channel configurable for BOP (HDLC/SDLC), COP (BISYNC), or ASYNC protocols. Each channel integrates a 16-bit multifunction counter/timer, digital phase-locked loop (DPLL), CRC/LRC generator/checker, and programmable encoding (NRZ/NRZI/FM0/FM1/Manchester).
It uses a synchronous bus interface compatible with 8086/iAPX86 MPUs, supporting polled, interrupt-driven, block-move, and DMA transfers-including dual-address and single-address DMA with EOPN frame termination signaling. The device powers from a single +5 V supply and operates from 0 °C to +70 °C.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Data Rate | Up to 10 Mbit/s per channel - enables high-speed legacy serial links without external rate-limiting logic. |
| FIFO Depth | 16-character receive/transmit FIFO per channel - reduces CPU interrupt/DMA overhead and prevents overrun/underrun in burst traffic. |
| Protocol Support | BOP (HDLC/SDLC/X.25), COP (BISYNC), ASYNC (5–8 bits + parity) - eliminates need for separate protocol-specific controllers. |
| Bit-Rate Sources | BRG (19 fixed rates), DPLL (≤312.5 kHz), counter/timer, or external 1X/16X clock - allows flexible clock sourcing for mixed-speed dual-channel operation. |
| Encoding Options | NRZ, NRZI, FM0, FM1, Manchester - supports legacy tape/disk controllers and telecom line coding requirements. |
| Bus Interface | Synchronous MPU interface (8086-compatible), 160 ns bus cycle - ensures direct drop-in integration with legacy x86-based industrial controllers. |
| Supply Voltage | +5 V ±10% - matches standard TTL/CMOS system rails without auxiliary regulation. |
Pinout & Package
SC26C562C1A,512 is housed in a 52-pin plastic leaded chip carrier (PLCC52, SOT238-2) with J-lead configuration and 0.050" pitch. The package is lead-free compatible and designed for surface-mount reflow assembly.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A1–A6 | Address Inputs | Select internal register address during MPU read/write cycles; active-HIGH, decoded via on-chip logic. |
| D0–D7 | Bidirectional Data Bus | 8-bit parallel interface for register access, command loading, and status/data transfer; 3-state when CSN inactive. |
| RDN / WRN | Read/Write Strobe | Active-LOW control signals synchronized with CSN to initiate register read or write; rising edge of WRN latches data. |
| CSN | Chip Select | Active-LOW enable for all data transfers; places D-bus in high-impedance when deasserted (except during interrupt/DMA cycles). |
| IRQN | Interrupt Request | Open-drain active-LOW output asserting on any enabled interrupt condition; supports vectorized or polled servicing. |
| RxDA/RxDB | Channel A/B Serial Input | Asynchronous/synchronous serial data inputs; sampled on rising edge of Rx clock when external clock selected. |
| TxDA/TxDB | Channel A/B Serial Output | Transmitted serial data outputs; least-significant bit first; held HIGH (marking) when disabled or in loopback. |
| X1/CLK, X2 | Oscillator Inputs | Crystal or external clock inputs; X1 accepts 0–16 MHz clock or crystal (with load caps); X2 is crystal return or floating for external clock mode. |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent protocol engines | Each channel independently programmable for BOP/COP/ASYNC - enables simultaneous HDLC telemetry and ASCII console on same IC. |
| Hardware-compatible with SCN26562 | PIN- and REGISTER-level compatibility with NMOS SCN26562 - allows drop-in replacement without PCB or firmware changes. |
| Programmable modem I/O | RTS/CTS/DCD pins configurable as general-purpose I/O or auto-enabled modem controls - simplifies board-level signal routing and protocol handshaking. |
| FIFO status bit appending | Receiver status and transmitter command bits appended to each FIFO character - enables atomic status-aware data reads without separate status polling. |
| DMA frame termination | EOPN signal asserts on terminal count or DMA DONE - ensures precise framing control for packetized data transfers without software intervention. |
Applications
| Industrial Protocol Converter | Legacy Telecom Terminal Interface |
|---|---|
Use Scenario: Converting RS-232 ASCII console traffic to HDLC-framed telemetry for SCADA backhaul over leased lines. IC Role / Device Role / Timing Role: SC26C562C1A,512 acts as dual-role serial bridge - Channel A handles async terminal I/O; Channel B performs HDLC framing, CRC generation, and synchronous line driving. Use Value: Eliminates need for two discrete UART + HDLC chips; leverages shared BRG and DMA to synchronize timing and reduce latency between domains. | Use Scenario: Interfacing a 68000-based PBX controller to T1/E1 line cards using X.25 link-layer framing. IC Role / Device Role / Timing Role: SC26C562C1A,512 provides X.25-compliant BOP engine with DPLL-based clock recovery and automatic zero insertion/deletion on Channel B. Use Value: Meets ITU-T X.25 physical layer timing tolerances (±0.01%) via integrated DPLL, avoiding external clock synthesis circuitry. |
| Embedded Disk Controller | Military Data Link Adapter |
Use Scenario: Managing synchronous serial communication between an 8086 host and magnetic tape drive using BISYNC protocol with SYN synchronization. IC Role / Device Role / Timing Role: SC26C562C1A,512 configures Channel A for dual-SYN BISYNC with external sync input (SYNIA) and programmable idle fill (MARK/SYN). Use Value: Supports legacy tape formats requiring precise byte-aligned sync detection and optional SYN stripping - validated in Philips CDUSCC User's Manual. | Use Scenario: Secure tactical radio interface requiring SDLC loop-mode operation with remote loop control and ABORT transmission. IC Role / Device Role / Timing Role: SC26C562C1A,512 runs Channel B in SDLC loop mode, using CTSBN as loop control output and generating 7/8-bit ABORT sequences on demand. Use Value: Enables deterministic loop activation/deactivation via hardware pin control, meeting MIL-STD-188-114A timing constraints for link reset. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual universal serial communications controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SCN26562C1A | NMOS process; higher power (ICC ≈ 120 mA vs. 80 mA); no on-chip oscillator; requires external clock source. | Same pinout/register map but lacks DPLL and crystal oscillator - unsuitable where clock recovery or crystal-based timing is required. | Select SCN26562C1A only if legacy NMOS board layout and external clock infrastructure already exist. |
| SC68C562C1A | Asynchronous bus interface (68000-compatible); different address/control timing; no RDYN signal; incompatible MPU handshake. | Designed for Motorola 68k systems - not electrically or logically compatible with 8086-based designs using SC26C562C1A,512. | Choose SC68C562C1A exclusively for 68000/68010 platforms; not a functional substitute in Intel-bus systems. |
Compared with SCN26562C1A and SC68C562C1A, the SC26C562C1A,512 uniquely combines 8086 bus compatibility, integrated crystal oscillator, DPLL-based clock recovery, and dual-protocol flexibility - making it the sole option for upgrading legacy NMOS DUSCC systems while adding timing autonomy and low-power operation.
Availability
SC26C562C1A,512 is available at Aetrix Electronics and suitable for industrial protocol conversion, legacy telecom terminal interfacing, and embedded disk controller applications requiring stable component supply across extended product lifecycles.
Supply support for SC26C562C1A,512 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT applications, with deep heritage in legacy logic and communications ICs acquired from Philips.
The SC26C562C1A,512 belongs to NXP's legacy Communications Controller product line, originally developed by Philips Semiconductors to replace discrete UART + protocol logic in industrial and telecom equipment - targeting long-lifecycle, reliability-critical embedded systems.
FAQ
Is SC26C562C1A,512 pin-compatible with SCN26562?
Yes, SC26C562C1A,512 is PIN- and REGISTER-compatible with SCN26562. It automatically defaults to the NMOS register map on power-up and shares identical PLCC52 pinout, enabling direct PCB replacement without layout changes. However, SC26C562C1A,512 adds on-chip oscillator and DPLL functionality not present in SCN26562.
What is the maximum supported crystal frequency for SC26C562C1A,512?
The SC26C562C1A,512 supports crystal or external clock frequencies up to 16.0 MHz on the X1/CLK pin, as specified in its AC Electrical Characteristics table. Operation at 14.7456 MHz is commonly used for standard UART baud rate derivation, and the device's internal oscillator circuitry is characterized for stable startup and jitter performance within this range.
Does SC26C562C1A,512 support both synchronous and asynchronous modes simultaneously?
Yes, SC26C562C1A,512 supports concurrent operation: Channel A can run in asynchronous mode (e.g., ASCII console) while Channel B operates in synchronous BOP mode (e.g., HDLC telemetry). Each channel's protocol, data format, clock source, and FIFO thresholds are independently programmable via dedicated register sets.
What are the key timing differences between SC26C562C1A,512 and SC68C562C1A?
SC26C562C1A,512 uses a synchronous bus interface (8086-compatible) with RDYN wait-state signaling, while SC68C562C1A uses an asynchronous interface (68000-compatible) with different strobe timing and no RDYN. Their address decoding, interrupt acknowledge sequences, and DMA handshake protocols are mutually incompatible - they cannot be substituted without redesigning MPU interface logic.
Can SC26C562C1A,512 generate Manchester-encoded output?
Yes, SC26C562C1A,512 supports Manchester encoding in both transmit and receive paths, with a maximum data rate of 5 MHz for Manchester-coded signals as specified in the AC Electrical Characteristics table. Encoding is selected per-channel via the Character Format Register (CFR), and the DPLL or BRG supplies the required bit-clock timing.
SC26C562C1A,512 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 52-LCC (J-Lead)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Applications:
- -
- Interface:
- DMA
- Voltage - Supply:
- 4.5V ~ 5.5V
- Supplier Device Package:
- 52-PLCC (19.15x19.15)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
SC26C562C1A,512 FAQ
1.How can I place an order for SC26C562C1A,512 through Aetrix?
Please submit a Request for Quotation (RFQ) for SC26C562C1A,512 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SC26C562C1A,512 reliable?
The price and inventory of SC26C562C1A,512 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SC26C562C1A,512 is usually 5 days.
3.What payment methods are accepted for SC26C562C1A,512?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SC26C562C1A,512 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SC26C562C1A,512?
SC26C562C1A,512 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SC26C562C1A,512 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SC26C562C1A,512?
For technical support, including SC26C562C1A,512 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SC26C562C1A,512 requirements.
6.How does Aetrix verify that SC26C562C1A,512 is sourced from the original manufacturer or authorized distributors?
All SC26C562C1A,512 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SC26C562C1A,512 meets industry standards.
7.What is the process for return or replacement of SC26C562C1A,512?
All SC26C562C1A,512 units undergo pre-shipment inspection (PSI). If there is an issue with SC26C562C1A,512, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SC26C562C1A,512 part is unused and in its original packaging.
Return procedure for SC26C562C1A,512:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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