NXP Semiconductors SC26C92C1B,557

Overview

SC26C92C1B,557 from NXP Semiconductors (formerly Philips) is a dual-channel CMOS universal asynchronous receiver/transmitter (DUART) with independent 8-character FIFOs per channel, programmable baud rates up to 230.4 kbaud, and full-duplex operation. It interfaces directly with microprocessors via an 8-bit parallel bus, supports interrupt- or polled-mode operation, and delivers robust serial communication for industrial control backplanes and legacy terminal systems.

For engineers reviewing the SC26C92C1B,557 datasheet, SC26C92C1B,557 pinout, SC26C92C1B,557 application, or SC26C92C1B,557 equivalent, key selection criteria include its 44-pin PQFP package, dual-channel independent clocking, hardware flow control via RTS/CTS, watchdog timers per receiver, and compatibility with SCC2692-based designs requiring extended FIFO depth and enhanced interrupt flexibility.

Technical Context

The SC26C92C1B,557 implements two independent UART channels sharing a common 8-bit data bus, address decoding (A0–A3), and chip enable (CEN) logic. Each channel features dedicated 8-byte transmit and receive FIFOs, programmable mode registers (MR0/MR1), and separate baud rate selection from 27 fixed rates (50–230.4 kbaud), counter/timer-derived rates, or external 1X/16X clocks.

Its timing subsystem integrates an on-chip crystal oscillator (X1/CLK, X2), a 16-bit programmable counter/timer, and four clock selectors enabling independent receiver/transmitter clock sourcing. The interrupt system provides one active-low open-drain INTRN output plus six wire-ORable outputs (OP3–OP7) configurable for Tx/Rx/counter events, with per-FIFO interrupt level thresholds and receiver watchdog timeout detection.

Key Specifications

Pinout & Package

SC26C92C1B,557 is housed in a 44-pin plastic quad flat pack (PQFP), SOT307-2, with 0.8 mm lead pitch and exposed thermal pad (not electrically connected). Pin 1 is located at top-left corner with index marking.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual UART applications.

Compared with SC26C92A1B, the SC26C92C1B,557 offers identical functionality at lower cost but excludes industrial-grade screening; compared with SCN2681C1B, it adds critical features including FIFO buffering, independent baud rate control, and hardware flow signaling - making it suitable for modern embedded serial gateways where throughput and robustness are essential.

Availability

SC26C92C1B,557 is available at Aetrix Electronics and suitable for industrial PLC backplanes, legacy terminal servers, multidrop terminal networks, and embedded modem interfaces requiring stable component supply across long production lifecycles.

Supply support for SC26C92C1B,557 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors, headquartered in Eindhoven, Netherlands, develops high-performance analog and mixed-signal ICs for industrial, automotive, and communications markets, with deep heritage in legacy Philips semiconductor technologies.

The SC26C92 product line was designed to extend the life of 1980s-era UART architectures with modern enhancements - specifically targeting backward-compatible upgrades for industrial control, point-of-sale, and telecom infrastructure where long-term availability and pin-level interoperability are mandatory.

FAQ

What is the primary function of the SC26C92C1B,557?

The SC26C92C1B,557 is a dual universal asynchronous receiver/transmitter (DUART) that provides two independent full-duplex serial communication channels. It handles parallel-to-serial and serial-to-parallel conversion, manages framing (start/stop/parity bits), buffers data in 8-character FIFOs per channel, and interfaces directly with microprocessors via an 8-bit data bus and control signals like WRN, RDN, and CEN. Its design targets industrial and legacy systems requiring reliable, interrupt-efficient serial I/O.

Does the SC26C92C1B,557 support hardware flow control?

Yes, the SC26C92C1B,557 supports hardware flow control through dedicated RTS/CTS signaling. OP0 and OP1 can be configured as active-low request-to-send outputs (RTSAN/RTSBN), while IP0 and IP1 serve as clear-to-send inputs (CTSAN/CTSBN). When enabled, the DUART automatically deasserts RTS when its receive FIFO reaches a programmable threshold, preventing buffer overflow from remote transmitters - a critical feature for high-throughput or variable-latency links.

What package type is used for the SC26C92C1B,557?

The SC26C92C1B,557 uses a 44-pin plastic quad flat pack (PQFP) package, designated SOT307-2. It features gull-wing leads with 0.8 mm pitch and includes two VCC pins (38 and 39) and one VSS pin (22) for improved power integrity. This surface-mount package supports automated PCB assembly and is pin-compatible with other SC26C92 variants in the same footprint, such as SC26C92A1B and SC26C92C1A.

Can the SC26C92C1B,557 operate with an external clock instead of a crystal?

Yes, the SC26C92C1B,557 accepts an external clock signal on the X1/CLK pin, eliminating the need for a crystal. The device supports clock frequencies from 0.1 MHz to 8 MHz, with 3.6864 MHz being optimal for standard baud rates. When using an external clock, X2 must be left unconnected or tied to ground. The internal oscillator circuitry remains functional but is bypassed, allowing direct synchronization to system-level timing sources for deterministic jitter performance.

How does the SC26C92C1B,557 handle interrupt generation?

The SC26C92C1B,557 provides flexible interrupt handling via a single active-low open-drain INTRN output and six additional interrupt-capable pins (OP3–OP7). Eight maskable conditions - including RxRDY, TxRDY, break detection, and counter/timer events - can trigger INTRN. OP3–OP7 may be individually assigned to specific interrupt sources and configured as open-drain outputs, enabling wire-OR configurations for multi-DUART systems without external logic. Each FIFO also supports four programmable interrupt threshold levels.