NXP Semiconductors SC26C92C1N,602

Overview

SC26C92C1N,602 from NXP Semiconductors (formerly Philips) is a dual-channel CMOS universal asynchronous receiver/transmitter (DUART) in a 40-pin plastic DIP package, operating from a single +5V supply. It provides two independent full-duplex UART channels with 8-character transmit and receive FIFOs, programmable baud rates up to 230.4 kbaud, and integrated crystal oscillator support - enabling robust serial communication in industrial control panels and legacy embedded systems requiring RS-232/RS-422 interface bridging.

For engineers reviewing the SC26C92C1N,602 datasheet, SC26C92C1N,602 pinout, SC26C92C1N,602 application, or SC26C92C1N,602 equivalent, key selection considerations include its dual-channel independence, per-channel 16-bit counter/timer clock sourcing, RTS/CTS flow control capability, watchdog timer per receiver, and compatibility with SCC2692-based legacy designs requiring deeper FIFOs and enhanced interrupt flexibility.

Technical Context

The SC26C92C1N,602 implements two fully independent UART channels (A and B), each with dedicated 8-byte FIFOs, programmable data format (5–8 data bits, 1/1.5/2 stop bits, odd/even/no parity), and separate baud rate selection from 27 fixed rates (50–230.4 kbaud), 16× clock derived from internal counter/timer, or external 1×/16× clock inputs. Its timing subsystem integrates an on-chip crystal oscillator (X1/CLK, X2), 16-bit programmable counter/timer, and four clock selectors for independent channel clock routing.

Interrupt handling uses a single active-low open-drain INTRN output with eight maskable sources, plus configurable OP3–OP7 pins as discrete wire-ORable interrupt outputs. The device supports automatic wake-up in multidrop mode, false start bit detection, line break generation/detection, and receiver timeout - all controlled via memory-mapped registers accessible through an 8-bit bidirectional data bus (D0–D7) and address lines A0–A3 under CEN/WRN/RDN strobes.

Key Specifications

Pinout & Package

SC26C92C1N,602 is housed in a 40-pin plastic dual in-line package (DIP), 0.6 inch wide, with 0.1 inch lead pitch. Pin 1 is index-corner marked; pins 22 (VSS) and 44 (VCC) provide ground and power respectively. All I/O pins are TTL-compatible with internal pull-ups on IP0–IP6.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual UART applications.

Compared with SCC2692C1N, SC26C92C1N,602 delivers significantly improved interrupt efficiency and noise resilience via FIFOs and watchdogs; versus TL16C550CP, it trades FIFO depth for self-contained timing and lower BOM count - making it optimal for cost-sensitive, space-constrained industrial boards where crystal integration matters.

Availability

SC26C92C1N,602 is available at Aetrix Electronics and suitable for industrial control panels, legacy terminal servers, medical diagnostic interfaces, and avionics ground test adapters requiring stable component supply and long-term obsolescence management.

Supply support for SC26C92C1N,602 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT applications, with roots in Philips' pioneering analog and mixed-signal design heritage.

The SC26C92C1N,602 belongs to NXP's legacy communications IC portfolio, designed specifically for industrial and telecom infrastructure requiring reliable, pin-compatible UART upgrades with enhanced buffering and timing autonomy.

FAQ

What is the maximum baud rate supported by the SC26C92C1N,602?

The SC26C92C1N,602 supports a maximum baud rate of 230.4 kbaud using its 27 fixed-rate table or programmable counter/timer-derived clocks. This is achieved in 16× sampling mode with a 3.6864 MHz crystal; actual data throughput remains limited to 230.4 kbit/s, not 1 Mbit/s - the latter refers to internal clock domain speed, not serial line rate.

Does the SC26C92C1N,602 require an external crystal or can it operate with an external clock?

Yes, the SC26C92C1N,602 can operate with either a 3.6864 MHz crystal connected between X1/CLK and X2, or an external clock applied to X1/CLK alone (X2 left open). The device's on-chip oscillator circuitry supports both configurations, and the clock input must meet AC specifications: 0.1–8 MHz frequency range and ≥50 ns high/low time.

How does the watchdog timer function in the SC26C92C1N,602?

The SC26C92C1N,602 includes a dedicated watchdog timer for each receiver channel that triggers upon absence of valid start bits over a programmable timeout interval. When activated, it asserts the corresponding RxRDY interrupt and sets status bits - allowing firmware to detect frozen or disconnected serial links without polling, which is essential in unattended remote monitoring systems.

Can the SC26C92C1N,602 be used in multidrop (9-bit) mode?

Yes, the SC26C92C1N,602 supports multidrop mode (also called 'wake-up' or '9-bit' mode) via programmable channel mode register settings. In this mode, the ninth bit distinguishes address frames from data frames, enabling selective activation of slaves on a shared bus - a feature confirmed in the device's mode register 1 (MR1) configuration and block diagram.

What is the purpose of the CEN pin on the SC26C92C1N,602?

The CEN (Chip Enable) pin on the SC26C92C1N,602 is an active-low signal that gates all data bus transactions. When high, it forces D0–D7 into high-impedance state, isolating the DUART from the microprocessor bus - enabling multi-device sharing without bus contention. It works in conjunction with WRN and RDN to define precise read/write timing windows per Philips' AC timing specifications.