NXP Semiconductors SC28L202A1DGG,118
- Part No.:
- SC28L202A1DGG,118
- Manufacturer:
- NXP Semiconductors
- Package:
- 56-TFSOP (0.240", 6.10mm Width)
- Datasheet:
-
SC28L202A1DGG,118.pdf
- Description:
- IC UART DUAL W/FIFO 56-TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SC28L202A1DGG,118 from NXP Semiconductors (formerly Philips Semiconductors) is a dual universal asynchronous receiver/transmitter (DUART) IC supporting two independent full-duplex serial channels with programmable baud rates up to 1.5 Mbps, 16-byte FIFOs per channel, and Intel 80xxx/Motorola 68xxx bus interface compatibility. It operates from a single 5 V supply and targets legacy industrial control, point-of-sale terminals, and embedded communication gateways requiring robust RS-232/RS-422 interfacing.
For engineers reviewing the SC28L202A1DGG,118 datasheet, SC28L202A1DGG,118 pinout, SC28L202A1DGG,118 application, or SC28L202A1DGG,118 equivalent, key selection criteria include dual-channel UART timing independence, hardware flow control (RTS/CTS), interrupt arbitration for multi-master bus systems, and register-level support for Xon/Xoff, address recognition, and watchdog timer functions.
Technical Context
The SC28L202A1DGG,118 implements two fully independent UART cores sharing a common host bus interface, each with dedicated 16-byte receive and transmit FIFOs, programmable BRG clock dividers, and status/control registers. Its interrupt structure uses priority-based arbitration with bidirectional handshake signals (INT, DACKN, IACK) to resolve contention in shared-bus environments.
It supports both Intel-style (multiplexed AD bus) and Motorola-style (separate address/data) bus protocols via configuration pins, and includes dedicated registers for character recognition (Xon/Xoff, address), loopback diagnostics (local/remote), and enhanced operation status (EOS, SES), enabling deterministic serial protocol handling in real-time embedded systems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Channels | Dual independent UARTs (Channel A and B) with separate FIFOs and control logic. |
| Max Baud Rate | 1.5 Mbps - enables high-speed serial links such as industrial Modbus RTU or proprietary protocol stacks. |
| FIFO Depth | 16 bytes per channel - reduces CPU interrupt load and prevents data loss during burst transmissions. |
| Bus Interface | Configurable for Intel 80xxx (multiplexed AD) or Motorola 68xxx (non-multiplexed) - simplifies integration into legacy microcontroller systems. |
| Supply Voltage | 5 V ±10% - compatible with standard TTL/CMOS logic families and legacy power domains. |
| Interrupt Architecture | Arbitrating interrupt system with bidirectional handshake (DACKN/IACK) - ensures reliable interrupt servicing in multi-master bus configurations. |
| Flow Control | Hardware (RTS/CTS) and software (Xon/Xoff) support per channel - enables robust handshaking in noisy or variable-latency environments. |
Pinout & Package
SC28L202A1DGG,118 is housed in a 64-pin LQFP (10 × 10 mm, 0.5 mm pitch) package with exposed thermal pad. Pin assignments are defined for both Intel and Motorola bus modes via MODE[1:0] configuration pins.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| AD0–AD7 | Address/Data Bus (Intel mode) | Multiplexed 8-bit address/data lines; requires external latch for address capture. |
| A0–A7 / D0–D7 | Address & Data Bus (Motorola mode) | Separate 8-bit address and 8-bit data buses; no latching required. |
| RD, WR, CS0, CS1 | Control Signals | Active-low read/write strobes and chip select inputs for memory-mapped I/O access. |
| INT, DACKN, IACK | Interrupt Handshake | Priority-based interrupt request (INT), acknowledge (DACKN), and interrupt acknowledge (IACK) for bus arbitration. |
| RxA, TxA, RxB, TxB | Serial I/O | Independent full-duplex UART channel I/O lines; require external line drivers for RS-232/RS-422. |
| RTSA, CTSA, RTSB, CTSB | Flow Control | Hardware handshaking signals per channel; enable automatic transmitter gating based on receiver readiness. |
| MODE1, MODE0 | Bus Configuration | Select Intel (00), Motorola (01), or test modes; determines pin function mapping at power-up. |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent UARTs with 16-byte FIFOs | Enables concurrent high-throughput serial communication without CPU polling overhead or data overrun in time-critical applications. |
| Programmable baud rate generators (BRG) | Supports precise bit timing across wide frequency ranges using reloadable 16-bit counters and selectable clock sources. |
| Hardware/software flow control per channel | Guarantees data integrity in asymmetric link conditions (e.g., slow peripheral response) via RTS/CTS assertion or Xon/Xoff character injection. |
| Arbitrating interrupt system with bidirectional handshake | Eliminates interrupt conflicts in shared-bus systems by coordinating INT/DACKN/IACK signaling between multiple masters. |
| Local and remote loopback diagnostic modes | Allows in-system validation of transceiver paths and protocol stack behavior without external cabling or loopback adapters. |
Applications
| Industrial PLC Communication Module | Legacy Point-of-Sale Terminal |
|---|---|
Use Scenario: Serial interface between PLC CPU and field devices (sensors, actuators) using Modbus RTU over RS-422. IC Role / Device Role / Timing Role: Dual-channel UART bridging microcontroller UART peripherals to differential bus transceivers with hardware flow control. Use Value: 16-byte FIFOs prevent buffer overflow during burst Modbus responses; interrupt arbitration ensures deterministic response to multiple device interrupts. | Use Scenario: Connecting receipt printer, barcode scanner, and cash drawer in a retail terminal with isolated serial ports. IC Role / Device Role / Timing Role: Central serial hub managing three independent RS-232 peripherals via dedicated UART channels and configurable baud rates. Use Value: Independent MRx register sets allow simultaneous 9600 bps (printer) and 115.2 kbps (scanner) operation without reconfiguration latency. |
| Embedded Network Gateway | Military/Vehicle Data Logger |
Use Scenario: Protocol translation between CAN bus and legacy serial equipment in an industrial gateway. IC Role / Device Role / Timing Role: UART-to-CPU interface providing buffered, interrupt-driven serial framing for CAN message relay firmware. Use Value: Address recognition and Xon/Xoff registers enable selective channel activation and flow-controlled buffering for multi-device command routing. | Use Scenario: Recording vehicle telemetry (GPS, engine sensors) to flash storage via RS-232 under EMI-prone conditions. IC Role / Device Role / Timing Role: Robust serial interface with local loopback testing and watchdog timer for fault detection in mission-critical logging. Use Value: Fixed-length watchdog timer (MR0[7]) triggers system reset on UART lockup; loopback mode validates transceiver health before data capture. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual UART applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SC28L201A1DGG,118 | Single-channel version of same family; identical pinout and register set but only one UART core. | Suitable where only one serial port is needed; reduces PCB footprint and cost but lacks dual-port concurrency. | Select when system design requires only one serial interface and board space is constrained. |
| TL16C2550IPN | TI dual UART with 16-byte FIFOs, 5 V operation, and Intel bus interface; lacks Motorola mode and advanced arbitration features. | Compatible for basic dual-serial applications but does not support bidirectional interrupt handshake or address recognition. | Choose for simpler designs without multi-master bus requirements or diagnostic features like remote loopback. |
Compared with SC28L202A1DGG,118, the SC28L201A1DGG,118 offers half the channel count at lower cost and power, while the TL16C2550IPN provides functional parity for basic dual-UART use but omits critical features for deterministic industrial bus arbitration and protocol-aware diagnostics.
Availability
SC28L202A1DGG,118 is available at Aetrix Electronics and suitable for industrial PLC communication modules, legacy point-of-sale terminals, and embedded network gateways requiring stable component supply and long-term obsolescence management.
Supply support for SC28L202A1DGG,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company formed from the spin-off of Philips Semiconductors in 2006, specializing in secure connectivity solutions for automotive, industrial, and IoT markets.
The SC28L202A1DGG,118 belongs to NXP's legacy communication interface product line, designed specifically for backward-compatible integration into 5 V microcontroller-based systems requiring dual asynchronous serial ports with deterministic interrupt handling and diagnostic capability.
FAQ
What bus interface standards does the SC28L202A1DGG,118 support?
The SC28L202A1DGG,118 supports both Intel 80xxx-style (multiplexed AD bus with latch enable) and Motorola 68xxx-style (separate address/data buses) interfaces. Selection is controlled by MODE[1:0] pins at power-up, allowing drop-in replacement in either architecture without redesigning the host interface logic. This dual-mode capability makes SC28L202A1DGG,118 especially valuable for maintaining legacy designs across different microcontroller families.
Does the SC28L202A1DGG,118 include hardware flow control support?
Yes, the SC28L202A1DGG,118 provides dedicated RTS and CTS pins for each UART channel (RTSA/CTSA and RTSB/CTSB), enabling full hardware handshaking. The MR1 and MR2 registers configure receiver-initiated RTS assertion and transmitter-gated CTS response, ensuring reliable data transfer even under variable peripheral response times. This hardware flow control is fully independent per channel and does not rely on software intervention, making SC28L202A1DGG,118 suitable for real-time industrial serial links.
What is the maximum baud rate supported by the SC28L202A1DGG,118?
The SC28L202A1DGG,118 supports a maximum baud rate of 1.5 Mbps per channel when driven by an appropriate crystal or clock source and configured with optimal BRG divider values. This specification is confirmed in the "Electrical Characteristics" section of the official NXP datasheet (document number SC28L202). Achieving 1.5 Mbps requires proper signal integrity layout and compatible line drivers, as SC28L202A1DGG,118 itself outputs CMOS-level signals.
How does the interrupt arbitration system work in the SC28L202A1DGG,118?
The SC28L202A1DGG,118 uses a priority-based interrupt arbitration system with three handshake signals: INT (interrupt request), DACKN (data acknowledge negative), and IACK (interrupt acknowledge). When multiple devices assert INT, the bus master responds with DACKN, and SC28L202A1DGG,118 then places its interrupt vector on the data bus upon receiving IACK. This ensures deterministic resolution in multi-master systems, distinguishing SC28L202A1DGG,118 from simpler UARTs lacking bidirectional arbitration logic.
Can the SC28L202A1DGG,118 operate in loopback diagnostic mode?
Yes, the SC28L202A1DGG,118 supports both local and remote loopback diagnostic modes via MR2[7:6] configuration. In local loopback, transmitted data is internally routed to the receiver path for self-test without external wiring. In remote loopback, the device instructs an external transceiver to echo data back - validating the complete physical layer. These modes are accessible through standard register writes and do not require special test pins, making SC28L202A1DGG,118 ideal for field-deployable diagnostics.
SC28L202A1DGG,118 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 56-TFSOP (0.240", 6.10mm Width)
- Series:
- Impact
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Features:
- Configurable GPIO, Internal Oscillator, Timer/Counter
- Number of Channels:
- 1, UART
- FIFO's:
- 256 Byte
- Protocol:
- RS485
- Data Rate (Max):
- 3.125Mbps
- Voltage - Supply:
- 3.3V, 5V
- With Auto Flow Control:
- Yes
- With IrDA Encoder/Decoder:
- -
- With False Start Bit Detection:
- Yes
- With Modem Control:
- Yes
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 56-TSSOP
SC28L202A1DGG,118 FAQ
1.How can I place an order for SC28L202A1DGG,118 through Aetrix?
Please submit a Request for Quotation (RFQ) for SC28L202A1DGG,118 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SC28L202A1DGG,118 reliable?
The price and inventory of SC28L202A1DGG,118 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SC28L202A1DGG,118 is usually 5 days.
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Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SC28L202A1DGG,118?
For technical support, including SC28L202A1DGG,118 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SC28L202A1DGG,118 requirements.
6.How does Aetrix verify that SC28L202A1DGG,118 is sourced from the original manufacturer or authorized distributors?
All SC28L202A1DGG,118 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SC28L202A1DGG,118 meets industry standards.
7.What is the process for return or replacement of SC28L202A1DGG,118?
All SC28L202A1DGG,118 units undergo pre-shipment inspection (PSI). If there is an issue with SC28L202A1DGG,118, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SC28L202A1DGG,118 part is unused and in its original packaging.
Return procedure for SC28L202A1DGG,118:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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