NXP Semiconductors SC28L92A1B,551

Overview

SC28L92A1B,551 from NXP Semiconductors is a dual-channel CMOS DUART operating at 3.3 V or 5.0 V, providing two independent full-duplex asynchronous serial channels with 16-byte receiver and transmitter FIFOs, programmable baud rates up to 230.4 kBd, and per-channel watchdog timers. It serves as a pin- and function-compatible upgrade to SC26C92 in industrial control panels requiring RS-232/422 interface consolidation.

For engineers reviewing the SC28L92A1B,551 datasheet, SC28L92A1B,551 pinout, SC28L92A1B,551 application, or SC28L92A1B,551 equivalent, this device delivers verified dual-channel UART functionality with Intel/Motorola bus selectability, FIFO depth configurability, and integrated crystal oscillator - critical for legacy microcontroller interfacing and multi-drop terminal systems.

Technical Context

The SC28L92A1B,551 implements two independent UART channels (A and B), each with fully programmable data format (5–8 data bits, 1/1.5/2 stop bits, odd/even/no parity), separate receiver/transmitter baud rate selection, and 16-bit programmable counter/timer supporting timer, counter, and time-out modes. Its timing architecture accepts either internal crystal (3.6864 MHz nominal) or external clock input at X1/CLK.

Pin-strapping via I/M determines bus interface mode: HIGH (or open) enables Intel 80xxx-style WRN/RDN control; LOW selects Motorola 68xxx-style R/WN/IACKN/DACKN protocol. MR0A[3] bit controls FIFO depth (8 or 16 bytes per channel), enabling strict SC26C92 compatibility when required.

Key Specifications

Pinout & Package

SC28L92A1B,551 is housed in a 44-pin plastic quad flat package (QFP44), SOT307-2, with 10 mm × 10 mm body and 1.3 mm lead length. Pin functions are identical across 80xxx and 68xxx bus modes, differing only in control signal assignment (WRN/RDN vs. R/WN/IACKN).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual UART applications.

Compared with SC26C92A1A,551 and TL16C550CPTR, the SC28L92A1B,551 uniquely combines dual-channel operation, selectable bus interface, on-chip oscillator, and per-channel watchdog - making it the only option for industrial upgrades requiring backward compatibility and enhanced reliability without board redesign.

Availability

SC28L92A1B,551 is available at Aetrix Electronics and suitable for industrial HMI terminals, legacy MCU communication bridges, multi-drop point-of-sale networks, and telecom line card management requiring stable component supply across extended product lifecycles.

Supply support for SC28L92A1B,551 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with deep heritage in communications ICs dating to Philips Semiconductor.

The SC28L92A1B,551 belongs to NXP's IMPACT family of 3.3 V/5 V UARTs designed for seamless migration from legacy SC26C92-based systems while adding FIFO depth, bus flexibility, and integrated timing - targeting industrial control, telecom infrastructure, and embedded instrumentation.

FAQ

What bus interface modes does the SC28L92A1B,551 support?

The SC28L92A1B,551 supports both Intel 80xxx and Motorola 68xxx bus interfaces, selected by the I/M pin: HIGH (or open) configures WRN/RDN control signals, while LOW enables R/WN/IACKN/DACKN protocol. This eliminates external bus translators in mixed-architecture systems and ensures direct compatibility with legacy 68k and x86 microcontrollers. The SC28L92A1B,551 maintains identical register mapping and timing across both modes.

How does the SC28L92A1B,551 handle FIFO depth configuration?

The SC28L92A1B,551 uses MR0A[3] bit to configure both channels' FIFO depth: logic 0 selects 8-byte mode (SC26C92-compatible), logic 1 enables 16-byte mode. This setting affects both Rx and Tx FIFOs simultaneously and automatically adjusts associated interrupt thresholds. The SC28L92A1B,551 powers up in 8-byte mode to ensure immediate SC26C92 firmware compatibility without register initialization.

Does the SC28L92A1B,551 include an integrated crystal oscillator?

Yes, the SC28L92A1B,551 integrates a crystal oscillator circuit supporting 3.6864 MHz nominal crystals (range up to 8 MHz) connected between X1/CLK and X2 pins. When using an external clock, X2 must be left open and X1/CLK driven directly. The SC28L92A1B,551 derives all internal timing-including baud rate generation and counter/timer-from this source, removing the need for external oscillator components.

What is the purpose of the watchdog timer in the SC28L92A1B,551?

The SC28L92A1B,551 includes a dedicated watchdog timer for each receiver channel that triggers upon absence of valid start bits over a programmable timeout period. This detects line faults, cable disconnects, or upstream transmitter failures in unattended systems like remote terminals. When asserted, it generates an interrupt and can be used to initiate recovery sequences-ensuring robust operation in industrial SC28L92A1B,551 deployments.

Can the SC28L92A1B,551 operate in multi-drop (9-bit) mode?

Yes, the SC28L92A1B,551 supports multi-drop (also called wake-up or 9-bit) mode via programmable channel mode registers. In this mode, it detects address characters (9th bit = 1) and data characters (9th bit = 0), enabling selective communication with multiple slaves on a shared bus. The SC28L92A1B,551 also provides start-end break interrupt and false start bit detection to enhance reliability in electrically noisy multi-drop environments.