My Inquiry
My Account
NXP Semiconductors SC28L92A1BS,557
- Part No.:
- SC28L92A1BS,557
- Manufacturer:
- NXP Semiconductors
- Package:
- 48-VFQFN Exposed Pad
- Datasheet:
-
SC28L92A1BS,557.pdf
- Description:
- IC UART DUAL W/FIFO 48HVQFN
- Quantity:
- Payment:
- Shipping:
Inventory:3,845
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SC28L92A1BS,557 from NXP Semiconductors is a dual-channel CMOS DUART operating at 3.3 V or 5.0 V, providing two independent full-duplex asynchronous serial channels with 16-character transmit and receive FIFOs, programmable baud rates up to 230.4 kBd (and 1 MHz in 16× mode), and per-channel watchdog timers. It serves as a pin- and function-compatible upgrade to SC26C92 in industrial control, telecom interface cards, and legacy system upgrades requiring enhanced FIFO depth and interrupt flexibility.
For engineers reviewing the SC28L92A1BS,557 datasheet, SC28L92A1BS,557 pinout, SC28L92A1BS,557 application, or SC28L92A1BS,557 equivalent, key selection considerations include its HVQFN48 package with thermal pad, dual-bus interface (68xxx/80xxx) configurability via I/M pin, 16-byte FIFO operation, and support for RS-232/RS-422 level-shifter interfacing in embedded communications subsystems.
Technical Context
The SC28L92A1BS,557 integrates two independent UART channels sharing a single 16-bit programmable counter/timer and crystal oscillator (3.6864 MHz nominal, up to 8 MHz). Each channel supports independent baud rate selection from 28 fixed rates or user-defined rates derived from the counter/timer, with 1× or 16× external clock inputs.
Its interrupt architecture features a single open-drain INTRN output with eight maskable conditions, plus optional discrete interrupt outputs on OP3–OP7. The device implements flow control via RTS/CTS signaling and includes a 7-bit multipurpose input port (with change-of-state detection on four lines) and an 8-bit multipurpose output port with individual bit set/reset capability.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 3.3 V ±10 % or 5.0 V ±10 % - supports mixed-voltage system integration without level shifters |
| FIFO Depth | 16-byte TX/RX per channel - reduces CPU interrupt overhead and prevents overrun/underrun in bursty traffic |
| Baud Rate Range | 50 kBd to 230.4 kBd (28 fixed rates); up to 1 Mbit/s with 16× clock - enables high-speed serial links in clustered terminal systems |
| Bus Interface | Pin-selectable 68xxx or 80xxx - eliminates need for bus translation logic in Motorola- or Intel-based designs |
| Operating Temperature | −40 °C to +85 °C - qualified for industrial and extended-temperature embedded applications |
| Package | HVQFN48 (6 × 6 × 0.85 mm, exposed thermal pad) - provides low thermal resistance and compact PCB footprint |
| Crystal Oscillator | On-chip, supports 3.6864 MHz nominal crystal or external clock up to 8 MHz - eliminates external oscillator component |
Pinout & Package
HVQFN48 package with 48 terminals, 6 mm × 6 mm body, 0.85 mm height, and exposed center thermal pad requiring solder connection to PCB ground plane for thermal and electrical integrity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC (pins 38,39,42) | Power supply | Accepts 3.3 V or 5.0 V - enables direct integration into either voltage domain without regulator |
| GND (pin 18 + exposed pad) | Ground reference | Exposed pad must be soldered to PCB ground plane - mandatory for thermal dissipation and signal integrity |
| I/M (pin 7) | Bus interface select | LOW = 68xxx mode (R/WN, IACKN, DACKN active); HIGH = 80xxx mode (WRN, RDN, RESET active) |
| RxDA (pin 31), RxDB (pin 5) | Serial data inputs | CMOS-level inputs compatible with RS-232/RS-422 transceivers - idle HIGH (Mark) logic state |
| TxDA (pin 30), TxDB (pin 8) | Serial data outputs | CMOS-level outputs - held HIGH when transmitter disabled or in loopback mode |
| INTRN (pin 19) | Interrupt request | Open-drain, active LOW - requires external pull-up; signals any of eight maskable conditions to host CPU |
| X1/CLK (pin 32), X2 (pin 33) | Clock input/output | Supports crystal (3.6864 MHz typical) or external clock up to 8 MHz - feeds baud rate generator and counter/timer |
| OP0–OP7 (pins 29,9,28,10,27,11,26,12) | Configurable I/O | Programmable as RTS/CTS, interrupt outputs (ISR[0]–[5]), or clock sources - enables flexible modem/DMA control |
Key Features
| Feature | Design Value |
|---|---|
| 16-byte per-channel FIFOs | Reduces interrupt frequency by >50 % vs. 8-byte FIFOs, enabling efficient polling or low-latency interrupt handling in real-time systems |
| Per-receiver watchdog timer | Detects stuck or silent serial lines and triggers interrupt - critical for fault-tolerant industrial communication links |
| Independent RX/TX baud rate programming | Enables dual-speed operation (e.g., 9600 bps RX / 115.2 kbps TX) required in multi-drop wake-up and clustered terminal architectures |
| 7-bit input port with change-of-state detection | Monitors up to four modem control lines (e.g., CTS, DSR) with hardware edge detection - offloads CPU polling |
| 8-bit output port with individual bit control | Allows atomic set/reset of RTS/CTS or status bits without read-modify-write cycles - prevents race conditions in interrupt service routines |
| Automatic echo and loopback modes | Supports self-test and diagnostic firmware without external loop wiring - accelerates validation of serial stack and PHY layer |
Applications
| Industrial PLC Serial Gateway | Legacy Telecom Interface Card |
|---|---|
Use Scenario: Connects Modbus RTU field devices to a 32-bit ARM controller via RS-485 transceivers. IC Role / Device Role / Timing Role: Dual-channel DUART handles simultaneous polling of two device chains, with independent baud rates and RTS-controlled half-duplex direction switching. Use Value: 16-byte FIFOs prevent overrun during burst reads from multiple sensors; watchdog timers detect cable faults before timeout cascades. |
Use Scenario: Adds two RS-232 ports to a TDM-based PBX line card for maintenance console and remote diagnostics. IC Role / Device Role / Timing Role: Provides full-duplex async channels with automatic echo for command-line interface, using internal crystal for stable timing across temperature. Use Value: Pin-compatible SC26C92 replacement allows drop-in upgrade; HVQFN48 saves board space vs. PLCC44 while maintaining thermal performance. |
| Medical Device Data Logger | Embedded Network Management Agent |
Use Scenario: Captures diagnostic logs from ECG and SpO₂ modules over isolated UART links to flash storage. IC Role / Device Role / Timing Role: Receives asynchronous telemetry at 115.2 kbps while transmitting status packets at 19.2 kbps - enabled by independent RX/TX rate configuration. Use Value: Flow control via RTS/CTS prevents buffer overflow during high-priority alarm transmission; power-down mode reduces standby current. |
Use Scenario: Enables out-of-band management on a switch ASIC via dedicated UART for firmware updates and debug access. IC Role / Device Role / Timing Role: Acts as dedicated serial controller with interrupt-driven DMA transfers, using OP4–OP7 as discrete interrupt lines for channel A/B event signaling. Use Value: Single INTRN pin simplifies interrupt routing; configurable output port drives LEDs and resets external transceivers synchronously with UART state. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual UART applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SC26C92B1A,557 | 8-byte FIFOs, no watchdog timer, SC28L92A1BS,557 pinout incompatible due to different package (PLCC44 vs HVQFN48) and bus timing | Limited to legacy designs requiring strict SC26C92 footprint and timing; lacks FIFO depth and reliability features | Select only if backward compatibility with existing PLCC44 layout and SC26C92 register map is mandatory |
| MAX3100EAP+T | SPI interface (not parallel), 128-byte FIFO, 3.3 V only, no 68xxx/80xxx bus option, integrated RS-232 drivers | Targets microcontroller-based systems with SPI peripherals; unsuitable for MPU bus interfacing or dual-voltage operation | Choose when replacing legacy parallel-interface UARTs with modern SPI-based designs and integrated level shifting |
Compared with SC26C92B1A,557 and MAX3100EAP+T, the SC28L92A1BS,557 uniquely delivers pin-configurable parallel bus support, dual-voltage operation, and 16-byte FIFOs in a thermally optimized HVQFN48 package - making it the only viable upgrade path for industrial MPU-based systems requiring enhanced serial throughput and reliability.
Availability
SC28L92A1BS,557 is available at Aetrix Electronics and suitable for industrial PLC gateways, telecom interface cards, medical data loggers, and embedded network management agents requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for SC28L92A1BS,557 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT applications, with deep expertise in mixed-signal and communications ICs.
The SC28L92A1BS,557 belongs to NXP's IMPACT family of universal asynchronous receiver/transmitters designed for robust, long-lifecycle industrial communications where pin compatibility, wide supply range, and thermal resilience are critical.
FAQ
What is the correct power-up sequence for SC28L92A1BS,557?
The SC28L92A1BS,557 requires no specific power sequencing between VCC and GND. Apply stable 3.3 V or 5.0 V within ±10 % tolerance, then assert RESET (HIGH in 80xxx mode, LOW in 68xxx mode) for ≥100 ns after power stabilizes. The device powers up emulating SC26C92 configuration, with MR0A[3] = 0 (8-byte FIFO default).
Does SC28L92A1BS,557 support RS-232 voltage levels directly?
No, SC28L92A1BS,557 provides CMOS-level serial I/O (RxDA, RxDB, TxDA, TxDB) and requires external RS-232 transceivers such as MAX3232 or SP3232. Its logic-high idle state (Mark) aligns with standard RS-232 driver input requirements, and it tolerates input voltages up to VCC + 0.5 V.
How is the HVQFN48 thermal pad of SC28L92A1BS,557 connected?
The exposed center pad of SC28L92A1BS,557 must be soldered to a PCB copper thermal pad tied to system ground. Thermal vias (≥4, 0.3 mm diameter) are required beneath the pad to conduct heat to inner or bottom ground planes. Failure to connect the pad compromises thermal performance and may cause functional instability.
Can SC28L92A1BS,557 operate with both channels at different bus interface modes?
No. The I/M pin configures the entire device for either 68xxx or 80xxx bus timing - both channels share the same interface mode. Pin 7 (I/M) must be hardwired to VCC (80xxx) or GND (68xxx); mixed-mode operation is not supported.
What is the maximum crystal frequency supported by SC28L92A1BS,557?
The SC28L92A1BS,557 supports crystal or external clock frequencies up to 8 MHz at the X1/CLK pin. At 8 MHz, the baud rate generator yields extended rates including 57.6 kBd, 115.2 kBd, and 230.4 kBd. All timing circuits - including counter/timer and FIFO logic - operate reliably within this limit.
SC28L92A1BS,557 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 48-VFQFN Exposed Pad
- Series:
- Impact
- Packaging:
- Tray
- Product Status:
- Obsolete
- Features:
- Configurable GPIO, Internal Oscillator, Timer/Counter
- Number of Channels:
- 2, DUART
- FIFO's:
- 16 Byte
- Protocol:
- -
- Data Rate (Max):
- 1Mbps
- Voltage - Supply:
- 3.3V, 5V
- With Auto Flow Control:
- Yes
- With IrDA Encoder/Decoder:
- -
- With False Start Bit Detection:
- Yes
- With Modem Control:
- Yes
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 48-HVQFN (6x6)
SC28L92A1BS,557 FAQ
1.How can I place an order for SC28L92A1BS,557 through Aetrix?
Please submit a Request for Quotation (RFQ) for SC28L92A1BS,557 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SC28L92A1BS,557 reliable?
The price and inventory of SC28L92A1BS,557 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SC28L92A1BS,557 is usually 5 days.
3.What payment methods are accepted for SC28L92A1BS,557?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SC28L92A1BS,557 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SC28L92A1BS,557?
SC28L92A1BS,557 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SC28L92A1BS,557 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SC28L92A1BS,557?
For technical support, including SC28L92A1BS,557 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SC28L92A1BS,557 requirements.
6.How does Aetrix verify that SC28L92A1BS,557 is sourced from the original manufacturer or authorized distributors?
All SC28L92A1BS,557 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SC28L92A1BS,557 meets industry standards.
7.What is the process for return or replacement of SC28L92A1BS,557?
All SC28L92A1BS,557 units undergo pre-shipment inspection (PSI). If there is an issue with SC28L92A1BS,557, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SC28L92A1BS,557 part is unused and in its original packaging.
Return procedure for SC28L92A1BS,557:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SC28L92A1BS,557 Tags
-
SC16IS741AIPWJ
NXP Semiconductors
-
TL16C550CPTR
Texas Instruments
-
TL16C550CIPTR
Texas Instruments
-
SC16C752BIB48,128
NXP Semiconductors
-
ST16C2550CQ48-F
MaxLinear, Inc.
-
ST16C2550CJ44-F
MaxLinear, Inc.
-
ST16C2552CJ44-F
MaxLinear, Inc.
-
ST16C1550IQ48-F
MaxLinear, Inc.
-
ST16C2550IQ48-F
MaxLinear, Inc.
-
ST16C554DIQ64-F
MaxLinear, Inc.
-
ST16C554DCQ64-F
MaxLinear, Inc.
-
XR17V352IB113-F
MaxLinear, Inc.
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
