Texas Instruments SCAN90CP02SP/NOPB
- Part No.:
- SCAN90CP02SP/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 28-UFQFN Exposed Pad
- Datasheet:
-
SCAN90CP02SP/NOPB.pdf
- Description:
- IC CROSSPOINT SW 1 X 2:2 28WQFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SCAN90CP02SP/NOPB from Texas Instruments is a 1.5 Gbps 2×2 LVDS crosspoint switch with IEEE 1149.1/1149.6 compliance, configurable 0/25/50/100% pre-emphasis per channel, and non-blocking pin-configurable routing (1:2 splitter, 2:1 mux, crossover, dual buffer). It operates from a single 3.3 V supply across −40°C to +85°C and targets high-reliability backplane and cable interconnects in telecom and datacom systems.
For engineers reviewing the SCAN90CP02SP/NOPB datasheet, SCAN90CP02SP/NOPB pinout, SCAN90CP02SP/NOPB application, or SCAN90CP02SP/NOPB equivalent, key selection criteria include differential jitter performance (≤126 psp-p TJ at 1.5 Gbps), independent channel enable/control, pre-emphasis programmability per output pair, and IEEE 1149.6 testability for AC-coupled high-speed links.
Technical Context
The SCAN90CP02SP/NOPB implements a flow-through, non-blocking crosspoint architecture with two independent differential input pairs (IN0±, IN1±) and two switched differential output pairs (OUT0±, OUT1±), each supporting LVDS, BLVDS, CML, and LVPECL signal levels. Configuration is controlled via four LVTTL select/enable pins (SEL0, SEL1, EN0, EN1), enabling eight defined functional modes including dual-channel repeater, 1:2 splitter, and crossover switching.
It integrates full IEEE 1149.1 boundary-scan logic for digital I/Os and IEEE 1149.6 cells on all differential inputs and outputs to support structural testing of high-speed AC-coupled interconnects up to 1.5 Gbps. Pre-emphasis is applied independently per output channel using two dedicated LVTTL control bits (PEM00/PEM01 for OUT0; PEM10/PEM11 for OUT1), with four discrete settings (0%, 25%, 50%, 100%) optimized for lossy media compensation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Data Rate | 1.5 Gbps per channel - supports serial links compliant with Fibre Channel, CPRI, and proprietary high-speed backplanes. |
| Differential Output Voltage (VOD) | 250–575 mV @ 100 Ω load - ensures robust LVDS signal integrity and noise margin in point-to-point topologies. |
| Total Jitter (TJ) | ≤126 psp-p (UQFN, 1.5 Gbps, PRBS223−1) - meets stringent timing budget requirements for multi-gigabit serial interfaces. |
| Supply Current | 42–60 mA (dual-channel active) - enables low-power operation in thermally constrained modules and line cards. |
| Pre-emphasis Control | 0/25/50/100% per channel - allows precise equalization tuning for varying trace lengths and connector losses without firmware overhead. |
| Operating Temperature | −40°C to +85°C - qualified for industrial and telecom infrastructure environments including base station RF units and packet switches. |
| Input Compatibility | LVDS, Bus LVDS, CML, LVPECL - eliminates level-shifting components when interfacing with TI SerDes, FPGAs, and ASIC transceivers. |
Pinout & Package
SCAN90CP02SP/NOPB is packaged in a 28-pin UQFN (NJD) with exposed thermal pad (DAP) serving as primary GND connection. The flow-through pinout minimizes signal path skew and simplifies PCB layout for high-speed differential routing.
| Pin | Circuit Role | Design Meaning |
|---|---|---|
| IN0+, IN0− | Differential Input Pair 0 | Accepts LVDS/BLVDS/CML/LVPECL signals; wide common-mode range (0.05–3.55 V) enables DC coupling to diverse drivers. |
| IN1+, IN1− | Differential Input Pair 1 | Independent second input channel; supports redundancy, diversity, or parallel data paths without internal contention. |
| OUT0+, OUT0− | Differential Output Pair 0 | Configurable destination for IN0 or IN1; pre-emphasis controlled by PEM00/PEM01; not multidrop-capable (point-to-point only). |
| OUT1+, OUT1− | Differential Output Pair 1 | Independent second output channel; pre-emphasis controlled by PEM10/PEM11; supports simultaneous dual-buffer operation. |
| SEL0, SEL1 | Routing Configuration Select | Two-bit encoding selects among eight defined modes (e.g., 00 = IN0→OUT0/OUT1 splitter; 10 = IN1→OUT0 / IN0→OUT1 crossover). |
| EN0, EN1 | Output Enable Controls | Per-output enable/disable; allows dynamic power gating and isolation of unused channels to reduce system-level power and crosstalk. |
| PEM00, PEM01, PEM10, PEM11 | Pre-emphasis Level Inputs | LVTTL-controlled 2-bit per-channel selection; enables real-time adaptation to channel loss without reconfiguration of core logic. |
| TDI, TDO, TCK, TMS, TRST | IEEE 1149.1 JTAG Interface | Full boundary-scan access to digital I/Os; integrated IEEE 1149.6 cells on differential I/Os enable structural test of high-speed AC-coupled nets. |
Key Features
| Feature | Design Value |
|---|---|
| Non-blocking 2×2 crosspoint | Enables simultaneous, independent routing of two high-speed data streams without arbitration delay or contention. |
| Per-channel pre-emphasis control | Reduces ISI-induced eye closure on lossy backplanes (>15-inch FR4) by applying tailored high-frequency boost to each output pair. |
| IEEE 1149.6 compliance | Supports production test of AC-coupled differential interconnects (e.g., capacitor-coupled traces) at full 1.5 Gbps data rates. |
| Flow-through pinout | Minimizes internal trace length and layer transitions, reducing package-induced jitter and easing impedance-controlled layout. |
| Single 3.3 V supply | Eliminates need for auxiliary voltage rails; simplifies power delivery design while maintaining LVDS-compatible output swing and noise immunity. |
Applications
| Telecom Line Card Signal Routing | High-Speed FPGA Interconnect |
|---|---|
Use Scenario: Reconfigurable signal distribution between multiple SerDes lanes on a carrier board and modular daughter cards in 5G baseband units. IC Role / Device Role / Timing Role: Crosspoint switch providing dynamic lane assignment, redundancy failover, and stub-hiding for clock/data recovery circuits. Use Value: Enables field-upgradable topology changes without hardware modification; pre-emphasis compensates for variable trace lengths across card-edge connectors. |
Use Scenario: Interfacing Xilinx Kintex Ultrascale+ FPGA transceivers to multiple optical module interfaces (SFP28, QSFP28) in packet aggregation switches. IC Role / Device Role / Timing Role: Signal repeater and multiplexer that restores signal integrity across long PCB runs and supports hot-plug detection via JTAG visibility. Use Value: Maintains <126 psp-p total jitter across 1.5 Gbps links, preserving BER <10−12; IEEE 1149.6 enables in-system validation of AC-coupled optical module connections. |
| Industrial Ethernet Backplane Switching | Test Equipment Signal Path Management |
Use Scenario: Redundant data path switching in PROFINET IRT or TSN-enabled motion control backplanes requiring sub-μs switchover. IC Role / Device Role / Timing Role: 2:1 redundancy multiplexer with <150 ns configuration time and <12 ns output disable latency for seamless failover. Use Value: Meets deterministic latency requirements for hard real-time networks; dual-channel operation supports parallel diagnostics and active monitoring. |
Use Scenario: Programmable signal routing inside automated test equipment (ATE) platforms handling mixed-signal DUTs with multiple high-speed interfaces. IC Role / Device Role / Timing Role: Reconfigurable signal conditioner and path selector that adapts test head wiring to different DUT pinouts and protocols. Use Value: Eliminates manual patch-panel reconfiguration; JTAG visibility enables automated continuity and short-circuit verification of differential test fixtures. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LVDS crosspoint switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX9159ETJ+ | 2×2 LVDS switch with fixed 50% pre-emphasis; no IEEE 1149.6 support; 1.35 Gbps max data rate. | Lacks AC-coupled interconnect testability; lower speed ceiling limits use in 1.5 Gbps+ designs. | Select when IEEE 1149.6 is unnecessary and cost sensitivity outweighs test coverage requirements. |
| SN65LVDS388AIPWPR | 4×4 LVDS crosspoint; no pre-emphasis; no JTAG; higher channel count but larger 48-pin TSSOP package. | Supports more complex routing but requires additional layout area and lacks signal conditioning for lossy media. | Select when scaling beyond 2×2 is needed and pre-emphasis/JTAG are secondary to channel density. |
Compared with MAX9159ETJ+ and SN65LVDS388AIPWPR, SCAN90CP02SP/NOPB uniquely combines per-channel programmable pre-emphasis, IEEE 1149.6 testability, and flow-through UQFN packaging-making it optimal for space-constrained, high-reliability 1.5 Gbps backplane applications where signal integrity and production test coverage are critical.
Availability
SCAN90CP02SP/NOPB is available at Aetrix Electronics and suitable for telecom infrastructure, industrial Ethernet gateways, and high-speed test equipment requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant UQFN packaging.
Supply support for SCAN90CP02SP/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and high-speed interface solutions, with decades of expertise in signal integrity and industrial-grade reliability.
The SCAN90CP02SP/NOPB belongs to TI's high-speed interface portfolio designed specifically for robust, testable, and reconfigurable differential signal routing in telecom, datacom, and industrial automation systems.
FAQ
What is the maximum supported data rate for SCAN90CP02SP/NOPB?
The SCAN90CP02SP/NOPB is characterized and specified for operation up to 1.5 Gbps per channel under recommended conditions (VDD = 3.3 V, TA = 25°C). Electrical specifications-including jitter (≤126 psp-p TJ), propagation delay (0.5–3.5 ns), and transition time (50–215 ps)-are guaranteed across this rate in both UQFN and LQFP packages. Operation beyond 1.5 Gbps is not supported or tested.
Does SCAN90CP02SP/NOPB support multidrop (BLVDS) bus topologies?
No, SCAN90CP02SP/NOPB does not support multidrop BLVDS environments. Its LVDS outputs are optimized for point-to-point connections only, with output characteristics tuned for backplane and cable applications. Attempting multidrop configurations may violate VOD and common-mode specifications and is explicitly excluded per datasheet Note (1) in the PIN DESCRIPTIONS section.
How is pre-emphasis configured on SCAN90CP02SP/NOPB?
SCAN90CP02SP/NOPB provides independent pre-emphasis control for each output channel via dedicated LVTTL input pairs: PEM00/PEM01 for OUT0± and PEM10/PEM11 for OUT1±. Each pair selects one of four discrete levels-0%, 25%, 50%, or 100%-as defined in Table 1 of the datasheet. No serial interface or register programming is required; configuration is static and pin-driven.
What package options are available for SCAN90CP02SP/NOPB?
SCAN90CP02SP/NOPB is offered exclusively in the 28-pin UQFN (NJD) package with an exposed thermal pad (DAP) used as the primary GND connection. While the base SCAN90CP02 family includes an LQFP-32 variant (SCAN90CP02VY/NOPB), the /NOPB suffix and part marking "SCP02SP" confirm this specific orderable number corresponds only to the UQFN-28 package.
Is IEEE 1149.6 test capability available on both differential inputs and outputs of SCAN90CP02SP/NOPB?
Yes, SCAN90CP02SP/NOPB integrates IEEE 1149.6-compliant test circuitry on all four differential I/Os: IN0±, IN1±, OUT0±, and OUT1±. This enables structural testing-including open/short detection-of AC-coupled high-speed interconnects at full operational data rates up to 1.5 Gbps, as confirmed in the DESIGN-FOR-TEST FEATURES section of the datasheet.
SCAN90CP02SP/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 28-UFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Crosspoint Switch
- Circuit:
- 1 x 2:2
- Independent Circuits:
- 1
- Current - Output High, Low:
- -
- Voltage Supply Source:
- Single Supply
- Voltage - Supply:
- 3V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-UQFN (5x5)
SCAN90CP02SP/NOPB FAQ
1.How can I place an order for SCAN90CP02SP/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for SCAN90CP02SP/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SCAN90CP02SP/NOPB reliable?
The price and inventory of SCAN90CP02SP/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SCAN90CP02SP/NOPB is usually 5 days.
3.What payment methods are accepted for SCAN90CP02SP/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SCAN90CP02SP/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SCAN90CP02SP/NOPB?
SCAN90CP02SP/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SCAN90CP02SP/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SCAN90CP02SP/NOPB?
For technical support, including SCAN90CP02SP/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SCAN90CP02SP/NOPB requirements.
6.How does Aetrix verify that SCAN90CP02SP/NOPB is sourced from the original manufacturer or authorized distributors?
All SCAN90CP02SP/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SCAN90CP02SP/NOPB meets industry standards.
7.What is the process for return or replacement of SCAN90CP02SP/NOPB?
All SCAN90CP02SP/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with SCAN90CP02SP/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SCAN90CP02SP/NOPB part is unused and in its original packaging.
Return procedure for SCAN90CP02SP/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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