Texas Instruments SCAN90CP02VY/NOPB
- Part No.:
- SCAN90CP02VY/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 32-LQFP
- Datasheet:
-
SCAN90CP02VY/NOPB.pdf
- Description:
- IC CROSSPOINT SW 1 X 2:2 32TQFP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SCAN90CP02VY/NOPB from Texas Instruments is a 1.5 Gbps 2×2 LVDS crosspoint switch with IEEE 1149.1/1149.6 JTAG test support, configurable 0/25/50/100% pre-emphasis per channel, non-blocking architecture, and dual 32-pin LQFP package. It operates from a single 3.3 V supply across −40°C to +85°C and delivers low output jitter (≤126 psp-p TJ at 1.5 Gbps) for high-integrity backplane and cable signal routing in telecom and datacom systems.
For engineers reviewing the SCAN90CP02VY/NOPB datasheet, SCAN90CP02VY/NOPB pinout, SCAN90CP02VY/NOPB application, or SCAN90CP02VY/NOPB equivalent, key selection considerations include differential input compatibility (LVDS/BLVDS/CML/LVPECL), programmable pre-emphasis for lossy media compensation, IEEE 1149.6 compliance for AC-coupled high-speed interconnect testability, and pin-configurable modes (1:2 splitter, 2:1 mux, crossover, dual repeater).
Technical Context
The SCAN90CP02VY/NOPB implements a fully non-blocking 2×2 crosspoint matrix with independent control of each output channel's enable (EN0/EN1) and pre-emphasis (PEM00/PEM01/PEM10/PEM11). Its flow-through pinout minimizes internal trace length and jitter accumulation, while integrated IEEE 1149.6 boundary-scan cells on all differential I/Os enable structural testing of AC-coupled high-speed links up to 1.5 Gbps.
Configuration is performed via LVTTL-level SEL0/SEL1 pins defining mode (e.g., dual repeater, 1:2 splitter), with separate power-down states per channel reducing static current to 1.4–2.5 mA. Input common-mode range spans 0.05 V to 3.55 V, supporting DC-coupled interfacing to LVPECL, CML, and LVDS drivers without level-shifting.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Max Data Rate | 1.5 Gbps per channel - supports full-rate serial links in telecom backplanes and FPGA-to-ASIC interconnects. |
| Differential Output Voltage (VOD) | 250–575 mV - meets LVDS standard compliance and ensures robust noise margin over 100 Ω termination. |
| Total Jitter (TJ) | ≤126 psp-p (UQFN) / ≤148 psp-p (LQFP) at 1.5 Gbps - guarantees bit-error-rate integrity in high-speed serial applications. |
| Supply Current (Dual Repeater) | 42–60 mA @ 3.3 V - enables low-power operation in thermally constrained industrial and embedded systems. |
| Pre-emphasis Levels | 0%, 25%, 50%, 100% per channel - compensates frequency-dependent loss in >10-inch FR4 traces or long cables. |
| Operating Temperature | −40°C to +85°C - qualified for industrial-grade deployment in base station, test equipment, and network infrastructure. |
| Package | LQFP-32 (NEY) - surface-mount compatible with JEDEC-standard reflow profiles and accessible for manual prototyping. |
Pinout & Package
SCAN90CP02VY/NOPB is packaged in a 32-pin LQFP (NEY) with exposed thermal pad (GND-connected DAP not present in LQFP variant). Pin assignments follow TI's standardized flow-through layout to minimize signal path skew and crosstalk.
| Pin | Circuit Role | Design Meaning |
|---|---|---|
| IN0+, IN0− | Differential Input Channel 0 | Accepts LVDS/BLVDS/CML/LVPECL signals; wide 0.05–3.55 V common-mode range enables direct DC coupling. |
| IN1+, IN1− | Differential Input Channel 1 | Independent second input pair; supports redundancy or parallel data streams without shared biasing. |
| OUT0+, OUT0− | Differential Output Channel 0 | LVDS-compliant outputs; individually enabled via EN0 and pre-emphasized via PEM00/PEM01. |
| OUT1+, OUT1− | Differential Output Channel 1 | Independent output pair; supports split-clock distribution or dual-data-path routing. |
| SEL0, SEL1 | Mode Configuration Inputs | Set crosspoint behavior: 1:2 splitter, 2:1 mux, crossover, or dual repeater - no external logic required. |
| EN0, EN1 | Output Enable Controls | Power-gate individual outputs to reduce system-level power consumption during idle or fault conditions. |
| PEM00–PEM11 | Pre-emphasis Control | Two-bit per-channel selection of 0/25/50/100% pre-emphasis - optimized for specific trace/cable loss profiles. |
| TDI/TDO/TCK/TMS/TRST | IEEE 1149.1 JTAG Interface | Enables boundary-scan testing of LVTTL pins and IEEE 1149.6 structural test of differential I/Os. |
| VDD, GND | Power & Ground | Single 3.3 V ±0.3 V supply; requires ≥4 × 0.01 µF low-ESR bypass capacitors per VDD pin group. |
Key Features
| Feature | Design Value |
|---|---|
| Non-blocking 2×2 Crosspoint Architecture | Enables simultaneous, independent routing of two differential data streams without contention or arbitration delay. |
| Configurable Per-Channel Pre-emphasis | Four discrete pre-emphasis levels (0–100%) per output allow precise equalization tuning for varying channel loss characteristics. |
| IEEE 1149.6 Compliance | Supports structural test of AC-coupled high-speed differential interconnects - critical for production test coverage in 1+ Gbps systems. |
| Flow-Through Pinout | Minimizes internal trace length and parasitic capacitance, reducing deterministic jitter and maintaining signal integrity at 1.5 Gbps. |
| Multi-Standard Differential Input Support | Interoperates with LVDS, Bus LVDS, CML, and LVPECL sources without external level shifters or terminations. |
Applications
| Telecom Backplane Signal Routing | High-Speed FPGA Interconnect |
|---|---|
|
Use Scenario: Routing 1.25 Gbps SerDes lanes between line cards and switching fabric in modular telecom chassis. IC Role / Device Role / Timing Role: 2×2 crosspoint switch providing flexible signal path selection, redundancy switching, and loss compensation via pre-emphasis. Use Value: Enables hot-swappable card architectures with <150 ns reconfiguration time and <126 psp-p total jitter for BER <10−12. |
Use Scenario: Interfacing multiple FPGA transceivers to a shared high-speed ADC/DAC or optical module interface. IC Role / Device Role / Timing Role: Dual-channel repeater and splitter managing clock/data fanout while preserving signal integrity across PCB layers. Use Value: Eliminates need for discrete buffer arrays; reduces BOM count by 60% and layout area by 45% versus discrete solutions. |
| Automated Test Equipment (ATE) | Industrial Camera Link Interface |
|
Use Scenario: Configurable signal path switching between DUT interfaces and high-speed digitizers in modular ATE platforms. IC Role / Device Role / Timing Role: IEEE 1149.6-enabled crosspoint enabling in-system structural test of differential probe connections and fixture wiring. Use Value: Reduces test development time by 35% through automated boundary-scan validation of >1 Gbps interconnects. |
Use Scenario: Adapting Camera Link Base/Medium/Full configurations by dynamically routing serialized pixel data and timing signals. IC Role / Device Role / Timing Role: 2:1 multiplexer selecting between dual camera inputs or 1:2 splitter distributing frame sync to multiple image processors. Use Value: Supports field-upgradable vision systems with zero hardware change - configuration updated via LVTTL control lines. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LVDS crosspoint switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX9159ETJ+ | 1.5 Gbps 2×2 LVDS switch with fixed 50% pre-emphasis; no IEEE 1149.6 support; TQFN-32 package. | Lacks structural test capability for AC-coupled links; suitable only where JTAG test coverage is not required. | Select when cost sensitivity outweighs testability requirements and pre-emphasis tuning flexibility is unnecessary. |
| SN65LVDS386DGGR | 2×2 LVDS repeater with no crosspoint switching or pre-emphasis; 800 Mbps max rate; VQFN-32 package. | Fixed repeater-only topology; cannot perform 2:1 mux or crossover functions; lower bandwidth limits use in 1.25+ Gbps systems. | Choose only for legacy 800 Mbps designs requiring minimal feature set and lowest unit cost. |
Compared with MAX9159ETJ+ and SN65LVDS386DGGR, SCAN90CP02VY/NOPB uniquely combines IEEE 1149.6 testability, per-channel pre-emphasis programming, and full non-blocking 2×2 routing - making it the sole option for production-testable, loss-compensated, reconfigurable high-speed interconnect in telecom and ATE.
Availability
SCAN90CP02VY/NOPB is available at Aetrix Electronics and suitable for telecom backplane routing, high-speed FPGA interconnect, automated test equipment (ATE), and industrial Camera Link interface applications requiring stable component supply and long-term industrial temperature support.
Supply support for SCAN90CP02VY/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and high-speed interface solutions with over 50 years of innovation in signal integrity and testability.
SCAN90CP02VY/NOPB belongs to TI's high-speed LVDS crosspoint switch product line, engineered specifically for testable, low-jitter, reconfigurable routing in 1+ Gbps backplane, datacom, and instrumentation systems.
FAQ
What is the maximum supported data rate for SCAN90CP02VY/NOPB?
SCAN90CP02VY/NOPB supports up to 1.5 Gbps per channel under recommended operating conditions (3.0–3.6 V supply, −40°C to +85°C). This is validated by characterization data showing ≤126 psp-p total jitter at 1.5 Gbps with PRBS223-1 pattern and 0% pre-emphasis in LQFP package. Operation beyond 1.5 Gbps is not characterized or guaranteed.
Does SCAN90CP02VY/NOPB support AC-coupled differential interfaces?
Yes, SCAN90CP02VY/NOPB supports AC-coupled differential interfaces on both inputs and outputs. Its wide common-mode input range (0.05 V to 3.55 V) and IEEE 1149.6 compliance explicitly enable structural testing of AC-coupled high-speed links - a key requirement for telecom and ATE applications using coupling capacitors on backplane traces.
How is pre-emphasis configured on SCAN90CP02VY/NOPB?
SCAN90CP02VY/NOPB provides independent 2-bit pre-emphasis control per output channel: PEM00/PEM01 for OUT0± and PEM10/PEM11 for OUT1±. These LVTTL inputs select 0%, 25%, 50%, or 100% pre-emphasis strength - documented in Table 1 of the SNLS168M datasheet - allowing precise compensation for channel loss without software overhead.
What package type is used for SCAN90CP02VY/NOPB?
SCAN90CP02VY/NOPB uses a 32-pin LQFP package (TI package code NEY), measuring 7.1 mm × 7.1 mm × 1.6 mm max height. It is RoHS-compliant, moisture-sensitivity Level-3 rated, and shipped in JEDEC trays (250 units per tray). Unlike the UQFN variant, this LQFP version has dedicated GND pins instead of an exposed thermal pad.
Is SCAN90CP02VY/NOPB compatible with LVPECL and CML signaling standards?
Yes, SCAN90CP02VY/NOPB accepts LVPECL and CML signals directly on its differential inputs (IN0±, IN1±) due to its wide 0.05–3.55 V common-mode voltage range and 100 mV minimum differential input voltage requirement. Figure 10 and Figure 11 in the SNLS168M datasheet show verified DC-coupled interface schematics for both standards.
SCAN90CP02VY/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 32-LQFP
- Packaging:
- Tray
- Product Status:
- Active
- Type:
- Crosspoint Switch
- Circuit:
- 1 x 2:2
- Independent Circuits:
- 1
- Current - Output High, Low:
- -
- Voltage Supply Source:
- Single Supply
- Voltage - Supply:
- 3V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-TQFP (7x7)
SCAN90CP02VY/NOPB FAQ
1.How can I place an order for SCAN90CP02VY/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for SCAN90CP02VY/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SCAN90CP02VY/NOPB reliable?
The price and inventory of SCAN90CP02VY/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SCAN90CP02VY/NOPB is usually 5 days.
3.What payment methods are accepted for SCAN90CP02VY/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SCAN90CP02VY/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SCAN90CP02VY/NOPB?
SCAN90CP02VY/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SCAN90CP02VY/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SCAN90CP02VY/NOPB?
For technical support, including SCAN90CP02VY/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SCAN90CP02VY/NOPB requirements.
6.How does Aetrix verify that SCAN90CP02VY/NOPB is sourced from the original manufacturer or authorized distributors?
All SCAN90CP02VY/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SCAN90CP02VY/NOPB meets industry standards.
7.What is the process for return or replacement of SCAN90CP02VY/NOPB?
All SCAN90CP02VY/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with SCAN90CP02VY/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SCAN90CP02VY/NOPB part is unused and in its original packaging.
Return procedure for SCAN90CP02VY/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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