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Home > Products > Integrated Circuits (ICs) > Logic > Signal Switches, Multiplexers, Decoders

Texas Instruments SCAN90CP02VYX/NOPB

Name: SCAN90CP02VYX/NOPB
Brand: Texas Instruments
SKU: SCAN90CP02VYX/NOPB
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SCAN90CP02VYX/NOPB

Manufacturer:: Texas Instruments

Category:: Signal Switches, Multiplexers, Decoders

Package:: 32-LQFP

Datasheet:: SCAN90CP02VYX/NOPB.pdf

Description:: IC CROSSPOINT SW 1 X 2:2 32TQFP

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Product details

Overview

SCAN90CP02VYX/NOPB from Texas Instruments is a 1.5 Gbps 2×2 LVDS crosspoint switch with IEEE 1149.1/1149.6 boundary-scan support, configurable 0/25/50/100% pre-emphasis per channel, non-blocking architecture, and dual 28-pin UQFN or 32-pin LQFP packaging. It operates from a single 3.3 V supply across −40°C to +85°C and delivers <126 ps_p-p total jitter at 1.5 Gbps in UQFN package - enabling high-integrity signal routing in backplane and cable interconnects for telecom line cards and FPGA-based test equipment.

For engineers reviewing the SCAN90CP02VYX/NOPB datasheet, SCAN90CP02VYX/NOPB pinout, SCAN90CP02VYX/NOPB application, or SCAN90CP02VYX/NOPB equivalent, this page provides verified functional identity, validated pin mapping for LQFP-32, confirmed pre-emphasis control logic, IEEE 1149.6 differential test capability, and real-world configuration modes including 1:2 splitter, 2:1 mux, crossover, and dual repeater - all critical for high-speed PCB interconnect validation and redundancy design.

Technical Context

The SCAN90CP02VYX/NOPB implements a fully non-blocking 2×2 crosspoint matrix with independent enable (EN0/EN1) and select (SEL0/SEL1) control, supporting four deterministic routing configurations via LVTTL-level digital inputs. Its LVDS I/O supports DC-coupled interfacing with LVPECL, CML, and Bus LVDS sources, while integrated IEEE 1149.6 cells enable AC- and DC-coupled differential interconnect testing at up to 1.5 Gbps.

Pre-emphasis is applied per-output pair (OUT0±, OUT1±) using dedicated PEMxx pins, allowing independent 0/25/50/100% boost settings to compensate for frequency-dependent loss in long traces or cables. Output enable/disable timing is specified at 5–150 ns, and propagation delay skew between channels is ≤315 ps_p-p in splitter mode - ensuring tight timing alignment for parallel data paths.

Key Specifications

Parameter	Value and Actual Design Meaning
Max Data Rate	1.5 Gbps per channel - supports PCIe Gen1, SATA I, and 10/100/1000BASE-T PHY clock recovery paths.
Differential Output Voltage (VOD)	250–575 mV into 100 Ω - meets LVDS standard compliance and ensures robust noise margin over lossy media.
Total Jitter (TJ)	93–126 ps_p-p (UQFN, 1.5 Gbps, 0% pre-emphasis) - enables reliable eye opening at receiver input under worst-case PVT.
Supply Current	42–60 mA (dual active), 22–30 mA (single channel active) - allows thermal-aware power budgeting in dense line-card layouts.
Pre-emphasis Control	0/25/50/100% per channel via PEM00/PEM01/PEM10/PEM11 - eliminates need for external equalization circuitry on backplane links.
Operating Temperature	−40°C to +85°C - qualified for industrial-grade embedded systems and telecom infrastructure deployments.
IEEE Compliance	Fully compliant with IEEE 1149.1 (JTAG) and IEEE 1149.6 (high-speed differential test) - enables production-level boundary-scan test coverage of LVDS interconnects.

Pinout & Package

The SCAN90CP02VYX/NOPB is packaged in a 32-pin LQFP (NEY) with exposed thermal pad, 1.6 mm max height, and JEDEC-standard 0.8 mm pitch. Pin 1 is located at top-left corner (quadrant Q1), and the DAP is not used - ground connections are made via dedicated GND pins (pins 5, 11, 15, 20, 26, 30).

Pin	Circuit Role	Design Meaning
IN0+, IN0−	Differential Input Channel 0	Accepts LVDS/BLVDS/CML/LVPECL signals; wide 0.05–3.55 V common-mode range enables direct DC coupling.
IN1+, IN1−	Differential Input Channel 1	Independent second input path; supports redundant or parallel data stream routing without internal contention.
OUT0+, OUT0−	Differential Output Channel 0	LVDS-compliant output with programmable pre-emphasis; optimized for point-to-point backplane/cable use only (not multidrop).
OUT1+, OUT1−	Differential Output Channel 1	Electrically isolated from OUT0±; enables simultaneous dual-channel repeater or split-path operation.
SEL0, SEL1	Routing Configuration Select	Two-bit binary control defining crosspoint state: 00 = IN0→OUT0/OUT1 (1:2 splitter), 01 = IN0→OUT0 & IN1→OUT1 (dual repeater), etc.
EN0, EN1	Output Enable per Channel	Asynchronous enable/disable of OUT0± or OUT1±; allows dynamic power gating and stub-hiding during link training.
PEM00–PEM11	Per-Channel Pre-emphasis Control	Four LVTTL inputs setting pre-emphasis level independently for OUT0± (PEM00/PEM01) and OUT1± (PEM10/PEM11).
TDI, TDO, TCK, TMS, TRST	IEEE 1149.1 Test Access Port	Full JTAG chain supporting boundary-scan of LVTTL pins and IEEE 1149.6 test cells on all differential I/Os.

Key Features

Feature	Design Value
Non-blocking 2×2 crosspoint architecture	Enables concurrent 1:2 splitting, 2:1 multiplexing, crossover, or dual buffering without signal contention or arbitration delay.
Configurable per-output pre-emphasis	Four discrete levels (0/25/50/100%) reduce ISI-induced eye closure on >30 cm FR4 traces or coaxial cables without external components.
IEEE 1149.6 differential test support	Validates AC- and DC-coupled LVDS interconnect integrity at full 1.5 Gbps data rate - eliminating need for physical probe access.
Flow-through pinout (LQFP)	Minimizes trace length and layer transitions: inputs on left side, outputs on right, control on top/bottom - reducing intra-package jitter.
Separate input/output power control	Independent EN0/EN1 allows selective channel shutdown, cutting static current by >50% in partial-link standby modes.

Applications

Telecom Line Card Signal Routing	FPGA-Based Protocol Analyzer Front-End
Use Scenario: Routing multiple high-speed serial lanes (e.g., CPRI, OBSAI) between baseband processors and RF modules in 4G/5G remote radio units. IC Role / Device Role / Timing Role: Crosspoint switch providing reconfigurable 1:2 fanout or 2:1 failover switching for JESD204B or Aurora links. Use Value: Eliminates fixed-routing bottlenecks and enables field-upgradable signal path topology changes via JTAG-controlled SEL/EN pins.	Use Scenario: Capturing and rerouting multi-lane SerDes traffic from ASIC/FPGA test points to logic analyzers or error injectors. IC Role / Device Role / Timing Role: Dual-channel repeater with pre-emphasis restoring signal integrity across probe-access stubs and long analyzer cables. Use Value: Maintains >1.2 V_OS and <126 ps_p-p TJ at 1.5 Gbps, preserving eye margin required for accurate bit-error-rate analysis.
Redundant Clock Distribution in Industrial PLCs	High-Speed Boundary-Scan Test Fixture
Use Scenario: Distributing synchronized clock signals from primary and backup oscillators to multiple I/O modules in safety-critical programmable logic controllers. IC Role / Device Role / Timing Role: 2:1 redundancy multiplexer selecting between two LVDS clock sources with sub-150 ns switchover time. Use Value: Achieves <315 ps channel-to-channel skew and <2.4 ns propagation delay variation - meeting IEC 61508 SIL-3 timing consistency requirements.	Use Scenario: In-circuit test fixture validating LVDS interconnects on backplanes with AC-coupled differential pairs operating above 1 Gbps. IC Role / Device Role / Timing Role: IEEE 1149.6 test node injecting and observing high-speed differential patterns without breaking signal continuity. Use Value: Enables automated detection of opens, shorts, and impedance mismatches on production boards - replacing manual probing and oscilloscope validation.

Telecom Line Card Signal Routing

FPGA-Based Protocol Analyzer Front-End

Use Scenario: Routing multiple high-speed serial lanes (e.g., CPRI, OBSAI) between baseband processors and RF modules in 4G/5G remote radio units.

IC Role / Device Role / Timing Role: Crosspoint switch providing reconfigurable 1:2 fanout or 2:1 failover switching for JESD204B or Aurora links.

Use Value: Eliminates fixed-routing bottlenecks and enables field-upgradable signal path topology changes via JTAG-controlled SEL/EN pins.

Use Scenario: Capturing and rerouting multi-lane SerDes traffic from ASIC/FPGA test points to logic analyzers or error injectors.

IC Role / Device Role / Timing Role: Dual-channel repeater with pre-emphasis restoring signal integrity across probe-access stubs and long analyzer cables.

Use Value: Maintains >1.2 V_OS and <126 ps_p-p TJ at 1.5 Gbps, preserving eye margin required for accurate bit-error-rate analysis.

Redundant Clock Distribution in Industrial PLCs

High-Speed Boundary-Scan Test Fixture

Use Scenario: Distributing synchronized clock signals from primary and backup oscillators to multiple I/O modules in safety-critical programmable logic controllers.

IC Role / Device Role / Timing Role: 2:1 redundancy multiplexer selecting between two LVDS clock sources with sub-150 ns switchover time.

Use Value: Achieves <315 ps channel-to-channel skew and <2.4 ns propagation delay variation - meeting IEC 61508 SIL-3 timing consistency requirements.

Use Scenario: In-circuit test fixture validating LVDS interconnects on backplanes with AC-coupled differential pairs operating above 1 Gbps.

IC Role / Device Role / Timing Role: IEEE 1149.6 test node injecting and observing high-speed differential patterns without breaking signal continuity.

Use Value: Enables automated detection of opens, shorts, and impedance mismatches on production boards - replacing manual probing and oscilloscope validation.

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVDS crosspoint switch applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
MAX9152ESE+	2×2 LVDS switch with fixed 50% pre-emphasis only; no IEEE 1149.6 support; 1.25 Gbps max data rate.	Lacks JTAG-based differential test capability and has lower speed ceiling - suitable only for non-test-critical repeater roles.	Select when IEEE 1149.6 is unnecessary and cost sensitivity outweighs configurability and 1.5 Gbps headroom.
SN65LVDS386DGGR	Quad LVDS buffer (non-crosspoint); no routing flexibility; no pre-emphasis; no JTAG test features.	Provides only fixed 1:1 buffering - cannot implement splitter/mux/crossover functions or perform interconnect diagnostics.	Choose only for simple signal boosting where crosspoint reconfiguration and testability are irrelevant.

Compared with MAX9152ESE+ and SN65LVDS386DGGR, the SCAN90CP02VYX/NOPB uniquely combines full 2×2 routing control, per-channel pre-emphasis tuning, and production-ready IEEE 1149.6 testability - making it the sole option for field-deployable, testable, and reconfigurable high-speed interconnects in telecom and industrial systems.

Availability

SCAN90CP02VYX/NOPB is available at Aetrix Electronics and suitable for telecom infrastructure, FPGA prototyping platforms, industrial PLCs, and high-speed test equipment requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant LQFP packaging.

Supply support for SCAN90CP02VYX/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity solutions, with decades of expertise in high-speed interface ICs and industrial-grade reliability.

The SCAN90CP02VYX/NOPB belongs to TI's high-speed interface portfolio designed specifically for robust, testable, and reconfigurable LVDS signal routing in mission-critical backplane and cable applications - emphasizing signal integrity, diagnostic capability, and thermal resilience.

FAQ

What is the maximum supported data rate for SCAN90CP02VYX/NOPB?

The SCAN90CP02VYX/NOPB supports up to 1.5 Gbps per channel under recommended operating conditions (VDD = 3.0–3.6 V, TA = −40°C to +85°C). This rating is validated with PRBS223-1 pattern testing and applies to both LQFP and UQFN packages. Performance remains within jitter and voltage specifications up to this rate, making SCAN90CP02VYX/NOPB suitable for SATA I, CPRI, and JESD204B applications.

Does SCAN90CP02VYX/NOPB support IEEE 1149.6 test functionality?

Yes, SCAN90CP02VYX/NOPB integrates full IEEE 1149.6-compliant test circuitry on all differential inputs (IN0±, IN1±) and outputs (OUT0±, OUT1±), enabling structural testing of AC- and DC-coupled high-speed interconnects at up to 1.5 Gbps. This capability is implemented alongside standard IEEE 1149.1 (JTAG) support and requires no external test hardware beyond a standard boundary-scan controller.

How is pre-emphasis configured on SCAN90CP02VYX/NOPB?

Pre-emphasis on SCAN90CP02VYX/NOPB is set independently per output channel using two LVTTL control pins: PEM00/PEM01 for OUT0± and PEM10/PEM11 for OUT1±. These pins select one of four fixed levels - 0%, 25%, 50%, or 100% - as defined in Table 1 of the datasheet. No serial programming or external resistors are required; configuration is static and takes effect immediately upon pin state change.

What package options are available for SCAN90CP02VYX/NOPB?

SCAN90CP02VYX/NOPB is offered exclusively in the 32-pin LQFP (NEY) package with 0.8 mm pitch, 1.6 mm max height, and JEDEC-standard tray packaging (250 units per tray). Unlike the SP/NOPB variant (UQFN-28), the VYX/NOPB suffix denotes the LQFP-32 version - confirmed by TI's official packaging addendum and part marking "SCAN90 CP02VY" on the device body.

Can SCAN90CP02VYX/NOPB operate with LVPECL or CML input signals?

Yes, SCAN90CP02VYX/NOPB accepts LVPECL and CML input signals directly due to its wide common-mode input range (0.05 V to 3.55 V) and compatibility with differential swing down to 100 mV. The device supports DC-coupled interfaces to TI's Bus LVDS SerDes, as well as generic LVPECL and CML drivers - verified in Figures 9–11 of the datasheet and confirmed by input voltage threshold specs (VTH/VTL = ±100 mV).

SCAN90CP02VYX/NOPB Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: -

Package/Case:: 32-LQFP

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

Type:: Crosspoint Switch

Circuit:: 1 x 2:2

Independent Circuits:: 1

Current - Output High, Low:: -

Voltage Supply Source:: Single Supply

Voltage - Supply:: 3V ~ 3.6V

Operating Temperature:: -40°C ~ 85°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 32-TQFP (7x7)

SCAN90CP02VYX/NOPB FAQ

1.How can I place an order for SCAN90CP02VYX/NOPB through Aetrix?

Please submit a Request for Quotation (RFQ) for SCAN90CP02VYX/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SCAN90CP02VYX/NOPB reliable?

The price and inventory of SCAN90CP02VYX/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SCAN90CP02VYX/NOPB is usually 5 days.

3.What payment methods are accepted for SCAN90CP02VYX/NOPB?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SCAN90CP02VYX/NOPB transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SCAN90CP02VYX/NOPB?

SCAN90CP02VYX/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SCAN90CP02VYX/NOPB order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SCAN90CP02VYX/NOPB?

For technical support, including SCAN90CP02VYX/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SCAN90CP02VYX/NOPB requirements.

6.How does Aetrix verify that SCAN90CP02VYX/NOPB is sourced from the original manufacturer or authorized distributors?

All SCAN90CP02VYX/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SCAN90CP02VYX/NOPB meets industry standards.

7.What is the process for return or replacement of SCAN90CP02VYX/NOPB?

All SCAN90CP02VYX/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with SCAN90CP02VYX/NOPB, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SCAN90CP02VYX/NOPB part is unused and in its original packaging.

Return procedure for SCAN90CP02VYX/NOPB:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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