Texas Instruments SCAN921023SLC

Overview

SCAN921023SLC from Texas Instruments (formerly National Semiconductor) is a 10-bit parallel-to-serial LVDS serializer IC designed for high-speed backplane and cable data transmission. It converts 10-bit LVCMOS/LVTTL data with embedded clock into a single 660 Mbps Bus LVDS serial stream, supports 20–66 MHz input clocks, features IEEE 1149.1 JTAG boundary-scan, and operates in a 49-ball BGA package rated for −40°C to +85°C.

For engineers reviewing the SCAN921023SLC datasheet, SCAN921023SLC pinout, SCAN921023SLC application, or SCAN921023SLC equivalent, key selection considerations include its 12-bit framing (10 data + 2 clock bits), flow-through BGA pinout, TRI-STATE enable via DEN/PWRDN, PLL lock time of 510 TCLK cycles, and guaranteed transition every 12-bit cycle for skew-free timing recovery.

Technical Context

The SCAN921023SLC implements a PLL-based serialization architecture that embeds clock information by appending start/stop bits to each 10-bit parallel word, producing a deterministic 12-bit frame at 12×TCLK rate. Its Bus LVDS output drives a 27 Ω differential load with 200–290 mV differential voltage and <35 mV unbalance.

It integrates IEEE 1149.1 test access port (TDI/TDO/TMS/TCK/TRST) and supports at-speed BIST via RUNBIST instruction for interconnect validation. Operation includes Initialization (PLL lock + SYNC pattern synchronization), Data Transfer (edge-triggered latching on TCLK_R/F), Powerdown (sub-500 µA ICCXD), and TRI-STATE (DEN-controlled driver disable).

Key Specifications

Pinout & Package

The SCAN921023SLC is housed in a 49-ball fine-pitch BGA (SLC49a) package with flow-through pinout optimized for minimal trace stubs and simplified PCB routing in backplane applications.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar serializer applications.

Compared with SCAN921023SLC, SN65LV1023A offers direct pin-and-function compatibility with measurable improvements in jitter and noise margin, while DS90CR285 serves a fundamentally different application space-requiring hardware redesign and sacrificing testability-making it unsuitable as a drop-in alternative.

Availability

SCAN921023SLC is available at Aetrix Electronics and suitable for backplane data links, cable-based instrumentation interconnects, IEEE 1149.1 test infrastructure, and hot-pluggable modular systems requiring stable component supply across extended product lifecycles.

Supply support for SCAN921023SLC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments acquired National Semiconductor in 2011 and maintains legacy product support, including datasheets, simulation models, and long-term supply commitments for industrial-grade analog and interface ICs.

The SCAN921023SLC belongs to TI's legacy Bus LVDS serializer family, engineered specifically for high-reliability, low-skew data transport in telecom, test equipment, and modular instrumentation where deterministic timing and built-in testability are critical.

FAQ

What is the maximum data payload rate supported by the SCAN921023SLC?

The SCAN921023SLC supports a maximum payload data rate of 660 Mbps, achieved when operating at its upper input clock limit of 66 MHz (10-bit × 66 MHz). Its gross serial rate is 792 Mbps (12-bit × 66 MHz), as two embedded clock bits are added per frame. This rate is validated under recommended conditions: VCC = 3.3 V, TA = +25°C, and RL = 27 Ω load.

Does the SCAN921023SLC require an external clock source for the deserializer to function?

No-the SCAN921023SLC itself does not require an external clock for the deserializer; it is the serializer only. However, the companion deserializer SCAN921224 requires a stable REFCLK input to recover the embedded clock. The SCAN921023SLC generates the serial stream containing clock information, but REFCLK must be supplied separately to the deserializer for proper lock acquisition and data recovery.

How does the SCAN921023SLC handle power-down and TRI-STATE modes?

The SCAN921023SLC supports two low-power states: PWRDN low disables the PLL and reduces supply current to ≤500 µA, while DEN low forces DO± into TRI-STATE. Both states preserve internal register contents. Exiting PWRDN requires high-going edge and 510 TCLK cycles for PLL relock; exiting DEN restores output drivers immediately if other controls remain static. These modes are fully documented in the Functional Description section of the SCAN921023SLC datasheet.

Can the SCAN921023SLC drive multiple receivers in a multi-drop configuration?

The SCAN921023SLC is specified for point-to-point connections and limited multi-drop backplanes. Its Bus LVDS output is rated for a 27 Ω load and exhibits degraded signal integrity with increasing stub lengths. Multi-drop use requires careful impedance matching, stub-length minimization (<1 inch per receiver), and validation of eye diagram margins at the farthest receiver. TI does not guarantee performance beyond point-to-point or short-stub topologies.

What JTAG instructions does the SCAN921023SLC support for interconnect testing?

The SCAN921023SLC supports two dedicated JTAG instructions for physical-layer validation: EXTEST (LVDS-level go/no-go test for opens/shorts) and RUNBIST (at-speed interconnect test with ~33 ms execution at 66 MHz). RUNBIST reports PASS/FAIL and TEST_COMPLETE via RX BIST data register bits, with pass defined as BER better than 10⁻⁷. Both instructions operate within the IEEE 1149.1 framework and require proper scan chain initialization.