Texas Instruments SCAN921025HSM/NOPB

Overview

SCAN921025HSM/NOPB from Texas Instruments is a high-temperature 10-bit parallel-to-serial LVDS Serializer IC designed for backplane and cable interconnects. It converts 10-bit LVCMOS/LVTTL data plus 2 control bits into an 800 Mbps Bus LVDS serial stream with embedded clock, supports 20–80 MHz input clock range, operates up to +125°C, and features IEEE 1149.1 JTAG compliance and at-speed BIST for aerospace-grade interconnect validation.

For engineers reviewing the SCAN921025HSM/NOPB datasheet, SCAN921025HSM/NOPB pinout, SCAN921025HSM/NOPB application, or SCAN921025HSM/NOPB equivalent, this page delivers verified electrical specs, PLL lock timing, Bus LVDS output drive capability (27 Ω load), synchronization mode behavior, and real-world hot-insertion and random-lock performance metrics - all confirmed from TI's SNLS185C datasheet.

Technical Context

The SCAN921025HSM/NOPB implements a PLL-based serialization architecture that embeds start/stop bits (10+2 framing) to generate a deterministic 12×TCLK serial rate - e.g., 960 Mbps at 80 MHz TCLK - while delivering 800 Mbps payload. Its Bus LVDS output complies with 27 Ω differential load requirements and guarantees transition every 12-bit cycle to prevent DC buildup on cables.

It operates in three active states (Initialization, Data Transfer, Resynchronization) and two passive states (Powerdown, Tri-state), with dedicated SYNC1/SYNC2 pins enabling deterministic lock acquisition (<0.8 μs at 80 MHz) or open-loop random-lock operation. JTAG test access and RUNBIST instruction support at-system-speed interconnect validation with BER <10⁻⁷.

Key Specifications

Pinout & Package

SCAN921025HSM/NOPB uses a 49-lead NFBGA package (7 mm × 7 mm, 0.8 mm pitch) with exposed thermal pad. Pin functions are validated per TI SNLS185C Figures 1, 8, 9, and Table 10.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 10-bit parallel-to-serial LVDS applications.

Compared with MAX9205+MAX9206 and DS90CR285, SCAN921025HSM/NOPB uniquely combines 10-bit precision, JTAG-accessible BIST, deterministic/random lock flexibility, and full military-grade temperature range - making it the only option qualified for safety-critical avionics and harsh-environment diagnostics.

Availability

SCAN921025HSM/NOPB is available at Aetrix Electronics and suitable for avionics backplane interconnects, automotive ADAS sensor hubs, industrial PLC I/O expansion, and military communications systems requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for SCAN921025HSM/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and high-reliability interface solutions for industrial, automotive, and aerospace markets.

The SCAN921025HSM/NOPB belongs to TI's high-temperature SerDes chipset family, engineered specifically for deterministic, low-skew, JTAG-testable data transmission across electrically noisy and thermally extreme backplane and cable environments.

FAQ

What is the maximum serial data rate supported by SCAN921025HSM/NOPB?

SCAN921025HSM/NOPB supports a maximum serial data rate of 960 Mbps, achieved at 80 MHz TCLK (12×TCLK framing). Its usable payload rate is 800 Mbps (10×TCLK), as two bits per frame are reserved for embedded clock recovery. This rate is fully characterized and guaranteed across −40°C to +125°C per TI SNLS185C.

Does SCAN921025HSM/NOPB require an external clock for the deserializer companion device?

Yes - SCAN921025HSM/NOPB itself does not provide the reference clock for its companion deserializer (SCAN921226H). The SCAN921226H requires a separate REFCLK input (20–80 MHz) to synchronize its PLL to the incoming Bus LVDS stream. SCAN921025HSM/NOPB generates only the serialized data and embedded clock bits; REFCLK must be supplied externally to the deserializer.

How does SCAN921025HSM/NOPB handle loss of synchronization during operation?

SCAN921025HSM/NOPB does not autonomously detect loss of sync - that function resides in the SCAN921226H deserializer, which asserts LOCK high upon losing PLL lock. However, SCAN921025HSM/NOPB supports rapid resynchronization: driving SYNC1 or SYNC2 high for ≥5×TCLK triggers immediate transmission of SYNC patterns, enabling the deserializer to relock in under 0.8 μs at 80 MHz.

Can SCAN921025HSM/NOPB operate without JTAG connectivity enabled?

Yes - JTAG functionality (TCK, TMS, TDI, TDO, TRST) is optional and does not affect core serialization operation. SCAN921025HSM/NOPB performs full LVDS serialization with or without JTAG signals connected. JTAG is used exclusively for boundary scan testing and RUNBIST execution; all timing, power, and data-path specifications remain valid with JTAG pins left unconnected or tied to inactive states.

What is the purpose of the TCLK_R/F pin on SCAN921025HSM/NOPB?

The TCLK_R/F pin selects the clock edge used to sample the DIN0–DIN9 parallel bus: logic high configures rising-edge sampling, and logic low configures falling-edge sampling. This allows SCAN921025HSM/NOPB to interface seamlessly with source ASICs or FPGAs that output data aligned to either clock phase - eliminating need for external delay elements or clock inversion.