Texas Instruments SCAN921226HSM/NOPB

Overview

SCAN921226HSM/NOPB from Texas Instruments is a 10-bit Bus LVDS deserializer IC that recovers parallel data and clock from a single differential serial stream, supporting 20–80 MHz input clock rates (800 Mbps payload), IEEE 1149.1 JTAG compliance, at-speed BIST, and operation up to +125°C. It serves as the receiver in high-reliability backplane or UTP cable interconnects for automotive and aerospace systems.

For engineers reviewing the SCAN921226HSM/NOPB datasheet, SCAN921226HSM/NOPB pinout, SCAN921226HSM/NOPB application, or SCAN921226HSM/NOPB equivalent, key selection criteria include embedded clock recovery performance, random-data lock time (<3.0 μs mean at 80 MHz), JTAG test access, tri-state control via REN, and compatibility with SCAN921025H serializer in chipset deployments.

Technical Context

The SCAN921226HSM/NOPB implements PLL-based clock recovery from a Bus LVDS serial stream containing 10 data bits + 2 embedded clock bits per 12-bit frame. It supports both synchronization-pattern–assisted lock (tDSR2 = 0.29–0.8 μs at 80 MHz) and random-data lock without SYNC patterns.

Its functional states include Data Transfer (LOCK low, ROUT0–ROUT9 valid), Resynchronization (LOCK high → low on relock), Powerdown (PWRDN/REN low, ICCR < 1.0 mA), and Tri-state (REN low, outputs high-impedance). JTAG TAP control enables boundary scan and RUNBIST interconnect testing at system speed.

Key Specifications

Pinout & Package

SCAN921226HSM/NOPB uses a 49-lead NFBGA package (7 mm × 7 mm, 0.8 mm pitch) with exposed thermal pad. Pin functions are validated per TI SNLS185C datasheet Figures 19–20 and Table 2.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar Bus LVDS deserializer applications.

Compared with MAX9205EEE+ and DS90CR288AMTDX/NOPB, SCAN921226HSM/NOPB uniquely integrates JTAG-compliant at-speed BIST, random-data lock capability, and extended temperature operation-making it the only option among the three qualified for safety-critical, high-reliability backplane applications requiring autonomous link validation and thermal robustness.

Availability

SCAN921226HSM/NOPB is available at Aetrix Electronics and suitable for automotive ADAS backplanes, industrial PLC I/O modules, and military avionics data links requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SCAN921226HSM/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies with over 50 years of high-reliability component design heritage.

The SCAN921226HSM/NOPB belongs to TI's high-temperature Bus LVDS SerDes chipset family, engineered specifically for deterministic, low-skew, JTAG-testable serial interconnects in harsh-environment automotive, industrial, and aerospace systems.

FAQ

What is the primary function of the SCAN921226HSM/NOPB in a SerDes system?

The SCAN921226HSM/NOPB is a 10-bit Bus LVDS deserializer that recovers parallel data and clock from a single differential serial stream. It works exclusively with the SCAN921025H serializer to form a complete chipset. Its core function is to extract embedded clock information from incoming Bus LVDS data (10 data + 2 clock bits/frame), regenerate a synchronous parallel output bus (ROUT0–ROUT9), and assert LOCK to indicate valid data alignment - all while supporting IEEE 1149.1 JTAG and at-speed BIST.

Does the SCAN921226HSM/NOPB require an external clock source, and if so, what are its requirements?

Yes, the SCAN921226HSM/NOPB requires a stable REFCLK input to operate. REFCLK must be supplied within 20–80 MHz, have a duty cycle of 30–70%, and meet transition time specifications (3–6 ns). This reference clock drives the internal PLL used for clock recovery and determines RCLK output timing. The device cannot achieve lock or produce valid ROUT data without an active REFCLK signal meeting these conditions.

How does the SCAN921226HSM/NOPB handle loss of synchronization during operation?

When the SCAN921226HSM/NOPB loses PLL lock - due to signal interruption, noise, or cable disconnect - the LOCK pin asserts high and ROUT0–ROUT9 enter invalid states. Recovery is initiated by pulsing SYNC1/SYNC2 on the paired SCAN921025H serializer to transmit synchronization patterns. The SCAN921226HSM/NOPB then reacquires lock in ≤0.8 μs (at 80 MHz), after which LOCK goes low and ROUT data resumes validity. No software reset or power cycle is required.

Can the SCAN921226HSM/NOPB operate without the SCAN921025H serializer?

No - the SCAN921226HSM/NOPB is designed exclusively for use with the SCAN921025H serializer as part of a matched chipset. Its Bus LVDS input expects a specific 12-bit framing format (10 data + 2 embedded clock bits), precise jitter tolerance, and timing alignment defined only by the SCAN921025H. While it can lock to random data patterns, interoperability, lock timing guarantees, and BIST functionality depend on the SCAN921025H's compliant output behavior.

What JTAG test capabilities does the SCAN921226HSM/NOPB support, and how are they implemented?

The SCAN921226HSM/NOPB fully implements IEEE 1149.1 JTAG with TCK, TMS, TDI, TDO, and TRST pins. It supports two dedicated test instructions: EXTEST (LVDS-level go/no-go interconnect check) and RUNBIST (at-system-speed interconnect validation with BER <10⁻⁷ pass threshold). RUNBIST executes in ~28 ms at 80 MHz and reports PASS/FAIL via RX BIST data register bits - enabling automated production and field diagnostics without external equipment.