Texas Instruments SCAN921226SLC/NOPB

Overview

SCAN921226SLC/NOPB from Texas Instruments (formerly National Semiconductor) is a 10-bit Bus LVDS deserializer IC that recovers parallel clock and reconstructs a 10-bit LVCMOS/LVTTL data bus from a single differential serial stream. It operates at 30–80 MHz input clock rates, delivers 800 Mbps payload data rate, supports IEEE 1149.1 JTAG boundary scan and at-speed BIST, and is used in high-integrity backplane and UTP cable interconnects for telecom and industrial control systems.

For engineers reviewing the SCAN921226SLC/NOPB datasheet, SCAN921226SLC/NOPB pinout, SCAN921226SLC/NOPB application, or SCAN921226SLC/NOPB equivalent, key selection criteria include embedded-clock recovery latency, random-lock capability under hot-insertion conditions, JTAG test access to differential interconnects, and power-down current <1 mA at 80 MHz.

Technical Context

The SCAN921226SLC/NOPB implements a PLL-based clock recovery architecture that locks to embedded clock bits (start/stop framing) within the 12-bit serialized stream (10 data + 2 clock bits). It accepts Bus LVDS input (RI±) with differential thresholds of ±6 mV to ±50 mV and drives CMOS/TTL outputs (ROUT0–ROUT9, RCLK, LOCK) with 15 pF load capability up to 80 MHz.

It supports three operational states-Data Transfer, Resynchronization, and Powerdown-and two passive states-TRI-STATE (via REN) and hot-insertion-ready random-lock mode. Its false-lock detection circuitry prevents mis-synchronization on repetitive multi-transition (RMT) patterns in DIN0–DIN8, ensuring robust lock acquisition on real-world data streams.

Key Specifications

Pinout & Package

SCAN921226SLC/NOPB is housed in a 49-lead BGA package (SLC49a), 7 mm × 7 mm, 0.8 mm pitch, with exposed thermal pad. Pin assignments are validated per National Semiconductor DS200248 (Rev. April 2004).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar deserializer applications.

Compared with SN65LVDS32 and DS90CR288A, SCAN921226SLC/NOPB uniquely integrates clock recovery, JTAG-accessible boundary scan, and at-speed BIST in a 10-bit BLVDS form factor - making it irreplaceable for high-integrity, self-testing backplane links requiring <1 µs resync and hot-insertion support.

Availability

SCAN921226SLC/NOPB is available at Aetrix Electronics and suitable for telecom backplane interconnects, industrial PLC I/O expansion, automotive ADAS sensor hubs, and automated test equipment requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SCAN921226SLC/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments acquired National Semiconductor in 2011 and maintains legacy product support, documentation, and qualification for high-reliability analog and interface ICs.

The SCAN921226SLC/NOPB belongs to TI's legacy Bus LVDS chipset family, designed specifically for high-speed, low-skew, testable parallel-to-serial bridging in mission-critical backplane and cable interconnect applications.

FAQ

What is the minimum REFCLK frequency supported by SCAN921226SLC/NOPB?

SCAN921226SLC/NOPB supports a minimum REFCLK frequency of 30 MHz, as specified in the Recommended Operating Conditions table. Operation below this frequency is not guaranteed - the PLL may fail to acquire or maintain lock, resulting in invalid ROUT outputs and persistent HIGH LOCK state. Designers must ensure REFCLK remains within 30–80 MHz across temperature and voltage variations.

Does SCAN921226SLC/NOPB require an external crystal or oscillator?

No, SCAN921226SLC/NOPB does not require an external crystal. It uses the externally supplied REFCLK signal (30–80 MHz) as its reference for PLL lock and clock recovery. The REFCLK must be a clean, low-jitter CMOS/TTL clock source - typically derived from a system clock generator or FPGA output - and must be active before power-up or exit from PWRDN mode.

How does SCAN921226SLC/NOPB handle loss of lock during data transmission?

When SCAN921226SLC/NOPB loses PLL lock, the LOCK pin goes HIGH and all ROUT outputs enter TRI-STATE. Up to three previously valid data cycles may contain bit errors due to delayed lock-detection logic. Recovery requires either resending SYNC patterns from the serializer or allowing random-lock acquisition - both methods are supported, with sync-based recovery completing in ≤0.8 µs at 80 MHz.

Can SCAN921226SLC/NOPB operate without JTAG connections?

Yes, SCAN921226SLC/NOPB functions fully in normal data mode with JTAG pins (TCK, TMS, TDI, TDO, TRST) unconnected or tied to valid logic levels. JTAG is optional and only required for boundary-scan testing or RUNBIST execution. All core deserialization functionality - including LOCK indication, ROUT output timing, and power-down control - operates independently of JTAG interface usage.

What is the maximum allowable stub length for SCAN921226SLC/NOPB on a backplane?

National Semiconductor recommends placing SCAN921226SLC/NOPB within <1 inch of the slot connector to minimize stub length. Longer stubs degrade impedance matching, increase Serializer loading, reduce threshold margin at the receiver, and impair signal integrity - especially at 800 Mbps. Layout best practices mandate controlled-impedance routing (100 Ω differential) and minimal via count between RI± and connector.