Texas Instruments SCAN921821TSM/NOPB
- Part No.:
- SCAN921821TSM/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Serializers, Deserializers
- Package:
- 100-LFBGA
- Datasheet:
-
SCAN921821TSM/NOPB.pdf
- Description:
- IC SERIALIZER DUAL 18BIT 100FBGA
- Quantity:
- Payment:

- Shipping:

Inventory:100
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Product details
Overview
SCAN921821TSM/NOPB from Texas Instruments is a dual-channel 18-bit parallel-to-serial LVCMOS/LVTTL-to-BLVDS serializer with embedded clock, 8-level pre-emphasis per channel, IEEE 1149.1 (JTAG) compliance, and at-speed BIST PRBS generation. It operates from 15–66 MHz (2.376 Gbps total throughput), delivers >15 kV HBM ESD protection on Bus LVDS I/O pins, and uses a single +3.3 V supply in an industrial −40°C to +85°C temperature range.
For engineers reviewing the SCAN921821TSM/NOPB datasheet, SCAN921821TSM/NOPB pinout, SCAN921821TSM/NOPB application, or SCAN921821TSM/NOPB equivalent, key selection considerations include dual-channel BLVDS serialization with pre-emphasis for lossy backplanes, JTAG test access, at-speed BIST for link integrity verification, and NFBGA-100 package compatibility with high-density routing constraints.
Technical Context
The SCAN921821TSM/NOPB integrates two independent serializer blocks, each with its own PLL (no external components required), dedicated TxCLK input, PWDN/EN/SYNC control, and 3-bit PEMx select lines enabling eight discrete pre-emphasis levels. Each channel converts 18-bit parallel data into a single differential BLVDS stream with embedded clock, eliminating clock-to-data skew and simplifying timing closure.
Its IEEE 1149.1 TAP controller supports boundary-scan testing and enables at-speed BIST via PRBS-15 pattern generation on either or both channels. The device features separate power domains-AVDD/DVDD/PVDD-with dedicated ground planes (AVSS/DVSS/PVSS)-and robust noise immunity via BLVDS signaling with 450–550 mV differential output voltage and <70 ps channel-to-channel skew.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Clock Rate | 15–66 MHz: Enables scalable serial link bandwidth from 270 Mbps to 2.376 Gbps per dual-channel system. |
| Total Throughput | 2.376 Gbps: Aggregate bidirectional capacity across both 18-bit serializers, sufficient for high-speed interconnects. |
| Pre-emphasis Levels | 8 selectable levels per channel: Compensates for frequency-dependent loss in cables/backplanes up to 10+ inches FR-4. |
| ESD Protection | >15 kV HBM on Bus LVDS pins: Ensures robust handling during board assembly and field deployment in industrial environments. |
| Supply Voltage | +3.3 V (3.15–3.45 V): Single-rail operation simplifies power delivery and eliminates level-shifting requirements. |
| Power Dissipation | 260 mW per channel (typ) at 66 MHz: Low active power supports thermal management in dense FPGA/ASIC interface applications. |
| Operating Temperature | −40°C to +85°C: Qualified for industrial-grade systems without derating or forced cooling. |
| Package | NFBGA-100 (NZD): 10 mm × 10 mm footprint with 0.8 mm ball pitch supports fine-pitch PCB routing and high I/O density. |
Pinout & Package
SCAN921821TSM/NOPB is housed in a compact 100-ball NFBGA (NZD) package with 0.8 mm ball pitch, optimized for high-speed signal integrity and thermal performance in space-constrained industrial and telecom modules.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| DINA0–17 / DINB0–17 | Parallel data inputs | Two independent 18-bit LVCMOS/LVTTL buses accepting source-synchronous parallel data for serialization. |
| DOUTAP/DOUTAN / DOUTBP/DOUTBN | Differential BLVDS outputs | Four dedicated LVDS output pairs delivering serialized streams with embedded clock and low EMI. |
| TxCLK | Reference clock input | Single-ended LVCMOS clock driving internal PLL and sampling parallel inputs; pull-up enabled by default. |
| PWDNA/PWDNB | Channel power-down control | Active-low pins disabling respective serializer, shutting down PLL, and reducing supply current to ≤3 mA per channel. |
| PEMA0–2 / PEMB0–2 | Pre-emphasis level select | 3-bit binary inputs selecting one of eight pre-emphasis gain settings per channel to compensate interconnect loss. |
| TDI/TDO/TMS/TCK/TRST | JTAG test interface | IEEE 1149.1-compliant boundary-scan port enabling structural testing and debug without physical probes. |
| BISTA/BISTB | BIST channel enable | Selects which serializer generates PRBS-15 patterns for at-speed link integrity validation. |
| AVDD/DVDD/PVDD | Power domain supplies | Separate analog (LVDS), digital (logic), and PLL/bias rails minimize noise coupling and improve jitter performance. |
Key Features
| Feature | Design Value |
|---|---|
| Dual 18:1 serialization | Reduces 36 parallel traces to 4 differential pairs, cutting PCB layer count and connector size while eliminating skew. |
| 8-level per-channel pre-emphasis | Adjustable high-frequency boost extends usable reach over FR-4 backplanes and coaxial cables beyond 1 meter. |
| Embedded clock architecture | Eliminates separate clock routing, removes clock-to-data skew, and simplifies timing analysis in high-speed designs. |
| At-speed BIST with PRBS-15 | Enables real-time link health monitoring and automated production test without external pattern generators. |
| Integrated PLL with no external components | Reduces bill-of-materials cost and layout area while maintaining <6.1 ps RMS random jitter at 66 MHz. |
| Robust BLVDS signaling | Delivers 450–550 mV differential swing with >15 kV HBM protection, ensuring reliable operation in noisy industrial environments. |
Applications
| High-Speed Backplane Interconnect | FPGA-to-FPGA Communication |
|---|---|
Use Scenario: Transmitting parallel video, sensor, or control data between line cards in modular telecom or test equipment chassis using FR-4 backplanes up to 12 inches long. IC Role / Device Role / Timing Role: Dual-channel serializer converting local FPGA parallel buses into robust, skew-free BLVDS streams with embedded clock for deterministic latency. Use Value: Enables 2.376 Gbps aggregate throughput with pre-emphasis compensation for insertion loss, reducing need for repeaters or equalizers. | Use Scenario: High-bandwidth data exchange between two FPGAs on the same PCB where trace length exceeds 8 inches and signal integrity degrades due to loss. IC Role / Device Role / Timing Role: Serializer bridging parallel AXI or custom interfaces, embedding clock to eliminate setup/hold violations across long traces. Use Value: Achieves sub-10 ps channel-to-channel skew and <6.1 ps RMS jitter, supporting reliable 66 MHz operation without retiming logic. |
| Automated Test Equipment (ATE) | Industrial Camera Link Interface |
Use Scenario: Driving high-speed digital stimulus and capture signals from ATE controller to DUT boards over multi-drop cabling with variable impedance. IC Role / Device Role / Timing Role: JTAG-configurable serializer providing at-speed BIST and boundary-scan visibility for fault isolation during production test. Use Value: Integrates IEEE 1149.1 TAP and PRBS-based link validation, reducing test time and eliminating external BERT equipment. | Use Scenario: Converting parallel image sensor output (e.g., CMOS imager) into serialized format compatible with Camera Link Base/Medium physical layer. IC Role / Device Role / Timing Role: Parallel-to-serial converter generating compliant BLVDS streams with programmable pre-emphasis for cable-driven camera links. Use Value: Supports up to 66 MHz pixel clocks and delivers >15 kV HBM protection on LVDS outputs, enhancing reliability in factory automation lighting environments. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel parallel-to-serial conversion applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN65LV1023A | Single-channel 24-bit serializer, no JTAG or BIST, fixed pre-emphasis, lower max clock (50 MHz). | Lacks dual-channel capability and diagnostic features; suitable only for simpler point-to-point links without testability needs. | Choose when cost sensitivity outweighs test coverage and channel count requirements. |
| DS90CR288A | 28-bit single-channel serializer with embedded clock, no pre-emphasis, no JTAG, 85 MHz max rate. | Higher bit-width but no dual-channel or built-in diagnostics; requires external clock recovery at receiver. | Select for higher-resolution parallel interfaces where dual serialization is unnecessary and test infrastructure is external. |
Compared with SN65LV1023A and DS90CR288A, SCAN921821TSM/NOPB uniquely delivers dual 18-bit serialization with integrated JTAG, at-speed BIST, and 8-level pre-emphasis-making it the only option for industrial backplane systems requiring concurrent link integrity verification and loss compensation.
Availability
SCAN921821TSM/NOPB is available at Aetrix Electronics and suitable for high-speed backplane interconnect, FPGA-to-FPGA communication, automated test equipment, and industrial camera link interface applications requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.
Supply support for SCAN921821TSM/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with decades of expertise in high-speed interface ICs and industrial-grade signal conditioning solutions.
The SCAN921821TSM/NOPB belongs to TI's high-speed serializer product line, designed specifically for deterministic, low-skew parallel-to-serial conversion in mission-critical industrial, telecom, and test equipment where signal integrity, testability, and long-term supply stability are mandatory.
FAQ
What is the maximum operating frequency of the SCAN921821TSM/NOPB?
The SCAN921821TSM/NOPB supports a clock rate range of 15 MHz to 66 MHz, delivering up to 2.376 Gbps total throughput across both channels. At 66 MHz, each 18-bit channel achieves 1.188 Gbps, verified under recommended operating conditions (3.15–3.45 V, −40°C to +85°C) with PRBS-15 pattern loading and worst-case load conditions.
Does the SCAN921821TSM/NOPB require external PLL components?
No, the SCAN921821TSM/NOPB integrates a fully self-contained PLL with no external components required. Its internal PLL locks to the TxCLK input and generates the precise high-speed serial clock needed for serialization, eliminating external crystals, capacitors, or loop filters and reducing design complexity and board area.
How does the pre-emphasis feature work on the SCAN921821TSM/NOPB?
The SCAN921821TSM/NOPB provides 8-level selectable pre-emphasis per channel via three control pins (PEMA0–2 or PEMB0–2). Each level adjusts the high-frequency content of the BLVDS output to counteract interconnect loss, with measured output voltage ratios (QPOV) ranging from 1.10× to 2.50× nominal VOD, enabling optimization for specific cable or backplane characteristics.
Is the SCAN921821TSM/NOPB compatible with IEEE 1149.1 (JTAG) boundary-scan?
Yes, the SCAN921821TSM/NOPB is fully IEEE 1149.1-compliant, featuring dedicated TDI, TDO, TMS, TCK, and TRST pins. Its integrated TAP controller supports boundary-scan instruction register access, data register scanning, and at-speed BIST activation-enabling structural testing and debug without modifying the application logic.
What package type and thermal characteristics does the SCAN921821TSM/NOPB use?
The SCAN921821TSM/NOPB uses a 100-ball NFBGA (NZD) package with 0.8 mm pitch, measuring 10 mm × 10 mm. Its thermal resistance is θJA = 35°C/W and θJC = 11.1°C/W, with a maximum junction temperature of +150°C and derating of 28.57 mW/°C above 25°C ambient, supporting reliable operation in convection-cooled industrial enclosures.
SCAN921821TSM/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 100-LFBGA
- Packaging:
- Tray
- Product Status:
- Active
- Function:
- Serializer
- Data Rate:
- 2.38Gbps
- Input Type:
- LVCMOS, LVTTL
- Output Type:
- LVDS
- Number of Inputs:
- 18
- Number of Outputs:
- 1
- Voltage - Supply:
- 3.15V ~ 3.45V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 100-FBGA (10x10)
SCAN921821TSM/NOPB FAQ
1.How can I place an order for SCAN921821TSM/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for SCAN921821TSM/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SCAN921821TSM/NOPB reliable?
The price and inventory of SCAN921821TSM/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SCAN921821TSM/NOPB is usually 5 days.
3.What payment methods are accepted for SCAN921821TSM/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SCAN921821TSM/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SCAN921821TSM/NOPB?
SCAN921821TSM/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SCAN921821TSM/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SCAN921821TSM/NOPB?
For technical support, including SCAN921821TSM/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SCAN921821TSM/NOPB requirements.
6.How does Aetrix verify that SCAN921821TSM/NOPB is sourced from the original manufacturer or authorized distributors?
All SCAN921821TSM/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SCAN921821TSM/NOPB meets industry standards.
7.What is the process for return or replacement of SCAN921821TSM/NOPB?
All SCAN921821TSM/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with SCAN921821TSM/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SCAN921821TSM/NOPB part is unused and in its original packaging.
Return procedure for SCAN921821TSM/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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