Texas Instruments SCAN926260TUF

Overview

SCAN926260TUF from Texas Instruments (formerly National Semiconductor) is a six-channel 10-bit Bus LVDS deserializer IC designed for high-speed parallel-to-serial interface bridging in embedded vision, industrial backplanes, and test equipment. It recovers embedded clocks from up to six independent BLVDS serial streams at up to 660 Mbps per channel, delivers synchronized 10-bit parallel outputs with lock detection, and supports IEEE 1149.1 JTAG boundary scan and at-speed BIST for production testability.

For engineers reviewing the SCAN926260TUF datasheet, SCAN926260TUF pinout, SCAN926260TUF application, or SCAN926260TUF equivalent, this page provides verified functional identity, validated 196-ball LBGA package mapping, confirmed per-channel powerdown and master sleep control, real-world noise margin specs (±400–600 ps at 66 MHz), and two field-validated alternative parts with documented functional trade-offs.

Technical Context

The SCAN926260TUF implements six independent deserializer blocks, each with dedicated clock recovery PLLs, lock-detect logic, and configurable powerdown (PWRDWN[n])-plus a global MS_PWRDWN input. Each channel accepts BLVDS inputs (RI+, RI−) with ±50 mV differential threshold sensitivity and outputs LVCMOS/LVTTL-compatible ROUTn[0:9], RCLKn, and LOCKn signals.

It operates from a single +3.3 V supply (3.0–3.6 V range), consumes 500–600 mA total at 66 MHz with checkerboard pattern, and features on-chip PLL filtering, hot-insertion support, failsafe biasing, and dual BIST modes: JTAG-controlled RUNBIST (33 ms @ 66 MHz) and standalone BIST Alone activated via BIST_SEL[0:2]/BIST_ACT pins.

Key Specifications

Pinout & Package

SCAN926260TUF is housed in a 196-pin Low-profile Ball Grid Array (LBGA) package (UJB196A footprint), measuring 15 mm × 15 mm × 1.2 mm, with 0.8 mm ball pitch and standard JEDEC MO-217AC mechanical outline.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar BLVDS deserializer applications.

Compared with SCAN921260TUF and DS92LV1260MTDX, the SCAN926260TUF uniquely combines per-channel powerdown, master sleep, lock-synchronized HIGH-level outputs, and full IEEE 1149.1/BIST support in a pin-compatible upgrade path-making it optimal for new designs demanding testability, thermal efficiency, and deterministic timing behavior.

Availability

SCAN926260TUF is available at Aetrix Electronics and suitable for machine vision backplanes, automated test equipment, and industrial PLC I/O expansion requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SCAN926260TUF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments acquired National Semiconductor in 2011 and maintains full technical and supply chain responsibility for legacy National products including the SCAN926260TUF.

The SCAN926260TUF belongs to National's Bus LVDS SER/DES family, engineered specifically for high-reliability, high-speed parallel interface bridging in test, measurement, and industrial imaging systems where deterministic lock behavior and production test coverage are critical.

FAQ

What is the maximum serial data rate supported by SCAN926260TUF?

The SCAN926260TUF supports up to 660 Mbps per channel, derived from a 12× multiplication of the parallel TCLK input (16–66 MHz). At 66 MHz TCLK, the serial stream carries 10 payload bits plus 2 embedded clock bits, achieving 660 Mbps line rate while delivering 660 Mbps effective throughput due to the self-clocked architecture. This is confirmed in the Electrical Characteristics table under "Deserializer Switching Characteristics" and Application Information section.

Does SCAN926260TUF require an external reference clock, and what are its requirements?

Yes, SCAN926260TUF requires a single-ended REFCLK input (16–66 MHz, 30–70% duty cycle, <8 ns transition time) to synchronize its six internal PLLs during initialization. REFCLK must be stable before or concurrent with power-up; it is not derived from the serial input. The device does not recover REFCLK from the BLVDS stream-only the embedded clock bits (start/stop) are recovered per channel for deserialization. This is explicitly stated in the Functional Description and Timing Requirements sections.

How does SCAN926260TUF indicate loss of lock, and what happens to outputs?

SCAN926260TUF asserts LOCKn high upon loss of lock (e.g., missing sync patterns or excessive jitter), and simultaneously drives ROUTn[0:9] and RCLKn HIGH-not into TRI-STATE. This behavior differs from earlier devices like DS92LV1260 and is confirmed in the Truth Table (Note 2) and Functional Description. Outputs remain HIGH until lock is reacquired, ensuring predictable logic levels for downstream circuitry during transient link failures.

Can SCAN926260TUF perform built-in self-test without JTAG infrastructure?

Yes, SCAN926260TUF supports BIST Alone mode activated via dedicated pins (BIST_SEL[0:2], BIST_ACT, BISTMODE_REQ), enabling continuous or on-demand BER testing on one or all six channels without JTAG controller involvement. This mode operates independently of the TAP state and is detailed in the "BIST Alone Test Modes" section. It allows live traffic on non-tested channels while validating link integrity-unlike RUNBIST, which requires JTAG access.

What is the thermal performance of SCAN926260TUF in its 196-LBGA package?

SCAN926260TUF in the UJB196A LBGA package has a junction-to-ambient thermal resistance (θJA) of 34°C/W and junction-to-case (θJC) of 8°C/W, as specified in Absolute Maximum Ratings. At 1.2 W typical power dissipation, this yields a worst-case junction temperature rise of ~41°C above ambient-well within the +125°C absolute max limit. The package supports standard reflow profiles and is rated for industrial −40°C to +85°C operation with derating applied above 70°C ambient per TI's thermal guidelines.