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Texas Instruments SCAN926260TUFX/NOPB

Part No.:
SCAN926260TUFX/NOPB
Manufacturer:
Texas Instruments
Category:
Serializers, Deserializers
Package:
-
Datasheet:
AetrixSCAN926260TUFX/NOPB.pdf
Description:
SCAN926260 SIX 1 TO 10 BUS LVDS
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Product details

Overview

SCAN926260TUFX/NOPB from Texas Instruments is a six-channel 1:10 Bus LVDS deserializer IC with integrated PLL clock recovery, IEEE 1149.1 (JTAG) compliance, and at-speed Built-In Self-Test (BIST). It accepts up to six independent 660 Mbps LVDS serial streams-each embedded with clock bits-and delivers synchronized 10-bit parallel outputs (ROUTn[0:9]) with recovered clocks (RCLKn) and lock-detect signals (LOCKn). Designed for high-reliability backplane and board-to-board interconnects in industrial imaging and test equipment.

For engineers reviewing the SCAN926260TUFX/NOPB datasheet, SCAN926260TUFX/NOPB pinout, SCAN926260TUFX/NOPB application, or SCAN926260TUFX/NOPB equivalent, key selection criteria include per-channel powerdown control, JTAG/BIST test coverage for interconnect validation, 16–66 MHz parallel clock rate support, 196-pin NFBGA package compatibility, and noise margin performance (±50 mV differential threshold) under real-world jitter conditions.

Technical Context

The SCAN926260TUFX/NOPB implements six independent deserializer blocks, each with its own PLL-based clock recovery circuitry, lock-detection logic, and dedicated PWRDWNn control. Each channel operates autonomously: it locks to incoming Bus LVDS data (e.g., from DS92LV1021/SCAN921025), recovers the embedded clock, and drives ROUTn[0:9] and RCLKn only when LOCKn is asserted low-ensuring data validity is strictly gated by lock status.

It supports dual test modes: IEEE 1149.1 boundary-scan (with EXTEST and RUNBIST instructions) and BIST Alone mode via dedicated pins (BIST_SEL[0:2], BIST_ACT, BISTMODE_REQ), enabling continuous BER testing on selected channels without disrupting live traffic on others. The device uses a single +3.3 V supply and features high-impedance inputs at VCC = 0 V.

Key Specifications

Parameter Value and Actual Design Meaning
Deserialization Ratio 1:10 - converts one serial LVDS stream into ten parallel CMOS/LVTTL data bits per channel.
Max Serial Data Rate 660 Mbps - supports TCLK up to 66 MHz × 12 (10 data + 2 framing bits).
Parallel Clock Range 16–66 MHz - defines valid output timing window for ROUTn/RCLKn synchronization.
Differential Input Threshold ±50 mV - enables robust operation against common-mode noise and ISI in long-trace or cable environments.
Supply Voltage +3.3 V (3.0–3.6 V range) - single-rail operation simplifies power delivery; 1.2 W typical dissipation at full load.
Operating Temperature −40°C to +85°C - qualified for industrial-grade embedded systems with thermal cycling requirements.
Package 196-pin NFBGA (12 mm × 12 mm, 0.8 mm pitch) - low-profile, high I/O density suitable for space-constrained PCB layouts.

Pinout & Package

SCAN926260TUFX/NOPB is housed in a 196-pin Low-Profile Ball Grid Array (NFBGA) package with 0.8 mm pitch and 12 mm × 12 mm footprint. Thermal resistance θJA = 34°C/W and θJC = 8°C/W support industrial thermal management.

Pin/Terminal Circuit Role Design Meaning
RI+[n], RI−[n] Bus LVDS Differential Input (per channel) Accepts serialized 10-bit data + embedded clock; ±50 mV threshold ensures reliable lock under jitter.
ROUTn[0:9] 10-bit Parallel Data Output (CMOS/LVTTL) Drives 15 pF load at 66 MHz; held HIGH when unlocked or in powerdown; tri-statable via REN.
RCLKn Recovered Clock Output (CMOS/LVTTL) Synchronous to ROUTn[0:9]; valid only when LOCKn = LOW; used for timing-critical destination ASIC interfaces.
LOCKn Channel Lock-Detect Output Active-low signal indicating PLL lock; gates data validity; unaffected by REN, enabling lock monitoring during tri-state.
PWRDWNn Per-Channel Powerdown Control Active-low input disabling individual deserializer block; reduces supply current ~80 mA per channel.
MS_PWRDWN Master Powerdown Control Active-low global sleep enable; overrides all PWRDWNn; forces all ROUTn/RCLKn/LOCKn HIGH.
REN Output Enable/Tri-State Control Active-high; places ROUTn[0:9] and RCLKn in high-impedance state while preserving LOCKn functionality.
REFCLK Reference Clock Input Single-ended CMOS/LVTTL input (16–66 MHz); used by internal PLL for local clock synthesis prior to data lock.
TCK, TMS, TDI, TDO, TRST JTAG Test Access Port Enables IEEE 1149.1 boundary-scan and RUNBIST interconnect testing; highest priority over functional controls.
BIST_SEL[0:2], BIST_ACT, BISTMODE_REQ BIST Alone Mode Control Enable channel-selectable, traffic-transparent BER testing without JTAG controller involvement.

Key Features

Feature Design Value
Independent Six-Channel Architecture Each deserializer operates autonomously with dedicated PLL, lock detection, and power control-enabling mixed-rate or partial-link operation.
At-Speed Interconnect BIST RUNBIST instruction executes in ~33 ms at 66 MHz system clock; reports per-channel PASS/FAIL with BER < 10⁻⁷ confidence.
Hot-Insertion Support High-impedance inputs at VCC = 0 V and failsafe biasing allow safe insertion/removal in powered-backplane systems following ground-first sequencing.
Per-Channel Power Management PWRDWNn pins reduce dynamic power by ~80 mA per idle channel; MS_PWRDWN provides system-level sleep coordination.
JTAG Priority Override SCAN_HIZB and SCAN_BIST signals force tri-state outputs regardless of REN/PWRDWN state-ensuring test integrity during debug.

Applications

Medical Imaging Backplane Automated Test Equipment (ATE)

Use Scenario: High-speed pixel data transfer from multi-sensor CT/MRI detector modules to FPGA-based image processors across rigid-flex backplanes.

IC Role / Device Role / Timing Role: Deserializes six independent 660 Mbps LVDS sensor streams into synchronous 10-bit parallel buses; RCLKn aligns sampling edges to minimize skew-induced artifacts.

Use Value: Enables deterministic latency (<1.75×RCLK period + 10 ns) and lock-gated data validity-critical for real-time reconstruction pipelines requiring sub-frame error detection.

Use Scenario: Interfacing multiple DUT (Device Under Test) sites to centralized pattern generators and capture logic in parallel test handlers.

IC Role / Device Role / Timing Role: Converts serialized stimulus/response data from TI Bus LVDS serializers into parallel format for real-time comparison; BIST Alone validates interconnect integrity per site without halting test flow.

Use Value: Per-channel BIST and lock monitoring allow concurrent diagnostics and production testing-reducing test floor downtime and improving yield analysis granularity.

Industrial Machine Vision Defense Radar Signal Processing

Use Scenario: Aggregating high-resolution line-scan camera outputs across modular vision controllers in robotic inspection cells.

IC Role / Device Role / Timing Role: Receives six asynchronous LVDS video streams; uses REFCLK-synchronized PLLs to recover clocks and deliver phase-aligned parallel data to SoC vision accelerators.

Use Value: ±50 mV differential threshold and on-chip PLL filtering tolerate EMI-rich factory environments-maintaining >99.999% link uptime during continuous 24/7 operation.

Use Scenario: Digitally interfacing phased-array radar front-end ADCs to beamforming FPGAs over extended PCB traces or twinax cabling.

IC Role / Device Role / Timing Role: Deserializes time-critical IF data streams with strict jitter tolerance; JTAG-compliant boundary scan supports field-upgradable test access in sealed enclosures.

Use Value: IEEE 1149.1 compliance and failsafe biasing meet MIL-STD-883 Class B reliability requirements-enabling in-system validation without physical probe access.

Equivalent & Alternatives

The following parts are listed as comparable options for similar Bus LVDS deserializer applications.

Alternative Part Technical Difference Application Difference Selection Advice
SCAN921260TUR Lacks BIST Alone mode; same JTAG/BIST core but no dedicated BIST_SEL/BIST_ACT pins; 66 MHz max parallel clock. No continuous per-channel BER testing during live traffic; requires JTAG controller for all BIST operations. Select when full JTAG infrastructure exists and BIST Alone is unnecessary; lower pin count simplifies layout.
DS92LV1260MTDX Max parallel clock 40 MHz; no JTAG or BIST; includes redundant seventh serial input channel. Not suitable for >40 MHz parallel bus interfaces; lacks standardized testability for high-mix ATE deployment. Select for cost-sensitive, lower-bandwidth applications where redundancy outweighs testability needs.

Compared with SCAN926260TUFX/NOPB, SCAN921260TUR trades BIST Alone flexibility for simpler control signaling, while DS92LV1260MTDX offers hardware redundancy at the expense of modern test infrastructure support-making SCAN926260TUFX/NOPB optimal for new designs demanding both speed and field-diagnosability.

Availability

SCAN926260TUFX/NOPB is available at Aetrix Electronics and suitable for medical imaging backplanes, automated test equipment, industrial machine vision systems, and defense radar signal processing requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SCAN926260TUFX/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with decades of expertise in high-speed interface ICs and industrial-grade reliability.

The SCAN926260TUFX/NOPB belongs to TI's Bus LVDS serializer/deserializer product line, engineered specifically for deterministic, low-jitter, high-density digital interconnects in mission-critical industrial and test instrumentation systems.

FAQ

What is the maximum serial data rate supported by SCAN926260TUFX/NOPB?

The SCAN926260TUFX/NOPB supports a maximum serial data rate of 660 Mbps, achieved when the parallel clock (TCLK) operates at 66 MHz and the serializer transmits 12-bit frames (10 data + 2 embedded clock bits). This rate is confirmed in the Electrical Characteristics table under "Deserializer Switching Characteristics" with tRCP = 15.15 ns minimum period, corresponding to 66 MHz RCLK operation.

Does SCAN926260TUFX/NOPB require an external reference clock, and what is its valid frequency range?

Yes, SCAN926260TUFX/NOPB requires a single-ended CMOS/LVTTL REFCLK input, specified for 16–66 MHz operation. This reference clock is used by each channel's internal PLL to synthesize a local clock before locking to the incoming LVDS data stream. The Recommended Operating Conditions table explicitly lists REFCLK frequency range and duty cycle (30–70%) requirements.

How does SCAN926260TUFX/NOPB indicate valid data output, and what happens when lock is lost?

SCAN926260TUFX/NOPB asserts LOCKn LOW only when its PLL has successfully locked to the incoming LVDS stream; ROUTn[0:9] and RCLKn outputs are guaranteed valid only during this state. Upon loss of lock-detected after two consecutive invalid clock edges-LOCKn goes HIGH and ROUTn[0:9]/RCLKn are driven HIGH (not tri-stated), providing fail-safe signaling for downstream logic to discard potentially corrupted data.

Can SCAN926260TUFX/NOPB perform built-in self-test without a JTAG controller?

Yes, SCAN926260TUFX/NOPB supports BIST Alone mode using dedicated pins (BIST_SEL[0:2], BIST_ACT, BISTMODE_REQ), allowing continuous or on-demand BER testing on one or all channels without engaging the JTAG TAP controller. This capability is documented in the "BIST Alone Test Modes" section and enables real-time diagnostics during live system operation.

What package type and thermal characteristics apply to SCAN926260TUFX/NOPB?

SCAN926260TUFX/NOPB uses a 196-pin NFBGA package (12 mm × 12 mm, 0.8 mm pitch) with θJA = 34°C/W and θJC = 8°C/W. These values are specified in the Absolute Maximum Ratings table and support industrial thermal design; the package is RoHS-compliant and marked with "TUFX/NOPB" per TI's packaging nomenclature.

SCAN926260TUFX/NOPB Specifications

Product attributes
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Manufacturer:
Texas Instruments
Series:
*
Package/Case:
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Packaging:
Bulk
Product Status:
Active
Function:
-
Data Rate:
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Number of Outputs:
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Operating Temperature:
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SCAN926260TUFX/NOPB FAQ

1.How can I place an order for SCAN926260TUFX/NOPB through Aetrix?

Please submit a Request for Quotation (RFQ) for SCAN926260TUFX/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

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The price and inventory of SCAN926260TUFX/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SCAN926260TUFX/NOPB is usually 5 days.

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5.How can I obtain technical support or documentation for SCAN926260TUFX/NOPB?

For technical support, including SCAN926260TUFX/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SCAN926260TUFX/NOPB requirements.

6.How does Aetrix verify that SCAN926260TUFX/NOPB is sourced from the original manufacturer or authorized distributors?

All SCAN926260TUFX/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SCAN926260TUFX/NOPB meets industry standards.

7.What is the process for return or replacement of SCAN926260TUFX/NOPB?

All SCAN926260TUFX/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with SCAN926260TUFX/NOPB, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SCAN926260TUFX/NOPB part is unused and in its original packaging.

Return procedure for SCAN926260TUFX/NOPB:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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