Texas Instruments SCAN928028TUF

Overview

SCAN928028 from Texas Instruments (formerly National Semiconductor) is an 8-channel 10:1 parallel-to-serial LVDS serializer with integrated IEEE 1149.1 JTAG and at-speed BIST. It accepts eight independent 10-bit LVTTL inputs synchronized to a single 18–66 MHz TCLK, serializes each into a 12-bit frame (10 data + start/stop clock bits), and outputs eight differential LVDS streams at up to 792 Mbps per channel (66 MHz × 12). It operates on a single +3.3V supply, dissipates 740 mW typical at 66 MHz, and targets high-reliability backplane and board-to-board interconnects in test equipment and industrial imaging systems.

For engineers reviewing the SCAN928028 datasheet, SCAN928028 pinout, SCAN928028 application, or SCAN928028 equivalent, key selection considerations include its 196-pin LBGA package, per-channel power-down control, PRBS-based @Speed Test capability for BER validation against SCAN921224/SCAN921226 deserializers, and strict timing requirements for tDIS (2.0 ns setup), tDIH (1.5 ns hold), and channel-to-channel skew (≤80 ps at 66 MHz).

Technical Context

The SCAN928028 implements eight independent 10:1 serializer blocks sharing one PLL and a common TCLK input-enabling synchronous serialization without inter-channel resynchronization overhead. Each channel embeds clock bits via start/stop framing and transmits at 12× TCLK rate, delivering deterministic payload throughput (e.g., 400 Mbps at 40 MHz TCLK).

Its test architecture integrates dual-layer verification: IEEE 1149.1 JTAG supports boundary-scan and RUN-BIST instructions for interconnect go/no-go and at-speed BER testing (pass threshold: <10⁻⁷), while the @Speed Test mode uses BIST_SEL[3:0] and BIST_ACT to route internally generated PRBS patterns to selected channels for end-to-end link validation with compatible deserializers.

Key Specifications

Pinout & Package

SCAN928028 is housed in a 196-pin Low-Profile Ball Grid Array (LBGA) package with 1.0 mm pitch, optimized for high-speed signal integrity and thermal dissipation (θJA = 34°C/W). The package supports controlled impedance routing and requires four-layer PCB construction with dedicated DVDD, PVDD, and AVDD power planes.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar parallel-to-serial LVDS conversion applications.

Compared with DS92LV1021, SCAN928028 reduces component count, eliminates clock skew between channels, and adds built-in testability; compared with standalone solutions, it trades flexibility for integration density and deterministic inter-channel timing-making it optimal for space-constrained, high-reliability systems requiring production-testable links.

Availability

SCAN928028 is available at Aetrix Electronics and suitable for medical imaging data acquisition, automated test equipment, industrial machine vision systems, and high-resolution digital video backplanes requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SCAN928028 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments acquired National Semiconductor in 2011 and maintains legacy product support, datasheets, and application notes for the SCAN928028 through ti.com.

The SCAN928028 belongs to National Semiconductor's BLVDS (Bus LVDS) serializer family, designed specifically for high-integrity, multi-channel parallel-to-serial conversion in test, measurement, and imaging systems where deterministic timing, low BER, and in-system testability are critical.

FAQ

What is the maximum serial data rate supported by SCAN928028?

The SCAN928028 serializes each 10-bit parallel input into a 12-bit frame (10 data + start/stop bits) at 12× the TCLK rate. With a maximum TCLK of 66 MHz, the serial output rate per channel is 792 Mbps. Aggregate bandwidth across all 8 channels is 6.336 Gbps, though payload remains 5.28 Gbps (66 MHz × 10 bits × 8). This rate is validated under PRBS loading and meets jitter specifications in the datasheet.

Does SCAN928028 require external clock conditioning for its PLL?

No-SCAN928028 includes on-chip PLL filtering optimized for PVDD supply noise rejection in the 300 kHz–1 MHz band. However, clean PVDD is essential: a CRC or CLC notch filter near the PVDD pin is recommended if the power supply exhibits switching noise in that range. The PLL locks to TCLK directly; no external VCXO or clock cleaner is needed for standard operation of SCAN928028.

How does SCAN928028 handle unused data bits when fewer than 10 bits are used per channel?

When using fewer than 10 bits (e.g., 8-bit mode), adjacent unused DINn pins must be tied to fixed logic levels to prevent repetitive-multiple-transition (RMT) patterns that impede deserializer lock. For example, tie DINn[0] high and DINn[9] low. This ensures the embedded clock edges remain detectable by SCAN921224/SCAN921226 deserializers and avoids false lock conditions during initialization of SCAN928028.

Can SCAN928028 operate with deserializers other than National Semiconductor parts?

SCAN928028 is explicitly designed for interoperability with National Semiconductor's SCAN921224, SCAN921226, SCAN921260, SCAN926260, DS92LV1210, DS92LV1212A, DS92LV1224, and DS92LV1260 deserializers. While other LVDS deserializers may accept the 12-bit framed stream, only these specified parts guarantee correct embedded clock recovery, SYNC pattern recognition, and @Speed Test PRBS verification-critical for full functionality of SCAN928028.

What is the purpose of the MS_PWDN and PWDNn pins on SCAN928028?

MS_PWDN is the master power-down control: driving it low disables the entire SCAN928028-including the shared PLL-and forces all DO± outputs into TRI-STATE. PWDNn (n = 0–7) provides per-channel power-down: asserting PWDNn disables only its associated serializer block while preserving PLL lock and operation of other channels. This allows dynamic bandwidth scaling-e.g., disabling unused channels in SCAN928028 to save ~6 mA per channel at 66 MHz-without disrupting active links.