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Texas Instruments SCANSTA112SM
- Part No.:
- SCANSTA112SM
- Manufacturer:
- Texas Instruments
- Category:
- Specialized
- Package:
- 100-LFBGA
- Datasheet:
-
SCANSTA112SM.pdf
- Description:
- IC INTERFACE SPECIALIZED 100FBGA
- Quantity:
- Payment:
- Shipping:
Inventory:4,295
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Product details
Overview
SCANSTA112SM from Texas Instruments is a 7-port IEEE 1149.1 (JTAG) multidrop multiplexer IC designed for hierarchical board-level test bus management. It supports up to 7 configurable local scan ports, bidirectional backplane/LSP0 slave/master switching, 32-bit TCK counter, and operates from 3.0–3.6 V over −40°C to +85°C. It enables system-level structural test and FPGA/ASIC programming in modular backplane systems.
For engineers reviewing the SCANSTA112SM datasheet, SCANSTA112SM pinout, SCANSTA112SM application, or SCANSTA112SM equivalent, key selection considerations include its addressable multidrop capability (up to 249 unique slot addresses), stitcher/transparent mode support, TRST-handling flexibility across 7 local ports, and NFBGA-100 packaging with live insertion support.
Technical Context
The SCANSTA112SM implements dual-level IEEE 1149.1 protocol extension: Level-1 for multidrop addressing (via S0–S7 slot inputs and ADDMASK) and Level-2 for per-port selection (LSPsel0–6) within a single device. Its TAP controller manages instruction register loading, mode register configuration (Mode0–3), and port enable logic for serial or grouped scan chain access.
It features bidirectional master/slave logic on B0/B1 backplane ports, TRI-STATE control via OE input, and dedicated pass-through I/O (A0B0/A1B0/Y0B0/Y1B0) for flash programming pulses or status monitoring. The 16-bit LFSR signature compactor and 32-bit TCK counter support built-in self-test during concurrent scan operations.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Function | IEEE 1149.1 multidrop JTAG multiplexer with hierarchical addressing and 7 local scan ports |
| Supply Voltage | 3.0–3.6 V - ensures compatibility with 3.3-V system rails and stable boundary-scan operation |
| Operating Temperature | −40°C to +85°C - qualified for industrial embedded and telecom backplane environments |
| Max Clock Frequency | 25 MHz - defines maximum vector shift rate in ScanBridge mode with full timing compliance |
| Package | NFBGA-100 (NZD) - 6×6 mm, 0.5-mm pitch, RoHS-compliant (NOPB.A variant), MSL Level-4 |
| TCK Counter | 32-bit - enables deterministic self-test execution timing and synchronization across multiple LSPs |
| LFSR Compactor | 16-bit - compresses test response data from selected local scan chains for efficient fault detection |
Pinout & Package
NFBGA-100 (NZD) package: 6 mm × 6 mm, 0.5 mm pitch, 10 × 10 array, bottom-side solder balls, thermal pad exposed on underside.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC (10 pins) | Power supply | Distributed power inputs for noise reduction and current sharing across core logic and I/O banks |
| GND (10 pins) | Ground reference | Multiple low-inductance ground connections for signal integrity and EMI control |
| TCKB0 / TCKB1 | Backplane clock input/output | Bidirectional TRI-STATE pins with hysteresis; master clock source for all scan operations when selected via MPselB1/B0 |
| TMSB0 / TMSB1 | Backplane mode select | Bidirectional TRI-STATE pins controlling TAP state transitions; drive strength 24 mA supports long backplane traces |
| TDIB0 / TDIB1 | Backplane data input | 25 kΩ internal pull-up; no ESD diode - requires external protection in live-insertion systems |
| TDOB0 / TDOB1 | Backplane data output | Bidirectional TRI-STATE outputs (12 mA); sampled during interrogation addressing for slot identification |
| S0–S7 | Slot address inputs | 8-bit parallel address bus defining unique identity in multidrop backplane (supports up to 249 distinct addresses) |
| LSPsel0–LSPsel6 | Local scan port select | 7-bit control enabling individual or grouped (2–3 port) inclusion of LSP0–LSP6 into active scan chain |
Key Features
| Feature | Design Value |
|---|---|
| True IEEE 1149.1 hierarchical & multidrop addressing | Enables selective communication with specific SCANSTA112SM devices in large backplane systems without bus contention |
| Bi-directional backplane and LSP0 ports | Allows alternate test master takeover via LSP0 while backplane becomes slave - critical for hot-swap test access |
| Stitcher Mode bypassing Level 1 & 2 protocols | Reduces setup latency by eliminating address decode and port selection steps - accelerates FPGA configuration sequences |
| Transparent Mode activation | Removes SCANSTA112SM registers from scan chain - enables reuse of legacy ATPG vectors generated for direct-connected devices |
| General-purpose pass-through bits (A/Y pairs) | Delivers precise write pulses to flash memory or monitors device status signals without requiring additional GPIO resources |
| TRST handling per local port | Independent TRST(01–06) outputs allow selective reset of individual ASIC/FPGA TAP controllers without affecting others |
Applications
| Board-Level JTAG Partitioning | Modular Backplane Test Systems |
|---|---|
Use Scenario: Partitioning a dense PCB with 12 FPGAs, 3 ASICs, and 2 microcontrollers into isolated scan chains. IC Role / Device Role / Timing Role: SCANSTA112SM acts as a programmable JTAG switch, routing test vectors from a single backplane controller to selected LSPs while isolating untested devices. Use Value: Reduces average test time by 40% versus flat-chain approach and improves fault isolation accuracy to individual device level. |
Use Scenario: System-level structural test across 8 plug-in cards in a telecom shelf, each hosting its own SCANSTA112SM. IC Role / Device Role / Timing Role: SCANSTA112SM serves as an addressable node in a multidrop backplane, responding only when its S0–S7 address matches the broadcast interrogation. Use Value: Enables board removal/replacement without disrupting test access to remaining modules - essential for field maintenance. |
| FPGA Configuration & Debug | Live Insertion/Withdrawal Support |
Use Scenario: Programming Xilinx Kintex FPGAs via JTAG during system boot, using same test infrastructure as production test. IC Role / Device Role / Timing Role: SCANSTA112SM provides buffered, synchronized TCK/TMS/TDI/TDO to LSP0–LSP6, with TRST control per device and pass-through A/Y bits for configuration status feedback. Use Value: Eliminates need for separate configuration hardware; leverages existing boundary-scan infrastructure for both test and firmware load. |
Use Scenario: Hot-plugging compute blades into a server chassis while maintaining JTAG visibility to installed modules. IC Role / Device Role / Timing Role: SCANSTA112SM's known power-up state, OE-controlled TRI-STATE outputs, and live-insertion qualification ensure safe electrical behavior during card insertion/removal. Use Value: Prevents bus contention and latch-up during hot-swap events - validated per TI's industrial reliability requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar JTAG multiplexing applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SCANSTA111SM | 6-port version; lacks LSP6, 32-bit TCK counter, and LFSR compactor; no stitcher mode | Supports smaller systems with ≤6 scan chains; no built-in self-test capability | Select when cost sensitivity outweighs need for 7th port or advanced diagnostics |
| SCANPSC110SM | Legacy 4-port predecessor; no multidrop addressing, no transparent/stitcher modes, no pass-through A/Y bits | Limited to point-to-point or simple daisy-chained topologies; no backplane scalability | Only for legacy redesigns where footprint and feature set match original PSC110-based architecture |
Compared with SCANSTA112SM, SCANSTA111SM reduces port count and diagnostic capability but lowers BOM cost, while SCANPSC110SM omits all multidrop and mode-flexibility features - making SCANSTA112SM the only option supporting scalable, addressable, and mode-adaptive JTAG infrastructure.
Availability
SCANSTA112SM is available at Aetrix Electronics and suitable for industrial backplane test systems, modular telecom equipment, FPGA-based compute blades, and high-reliability embedded systems requiring stable component supply and long-term lifecycle support.
Supply support for SCANSTA112SM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with decades of leadership in test and debug silicon.
The SCANSTA112SM belongs to TI's IEEE 1149.1 infrastructure product line, engineered specifically for scalable, addressable JTAG test bus architectures in modular, hot-swappable, and high-density electronic systems.
FAQ
What is the primary function of the SCANSTA112SM in a JTAG test architecture?
The SCANSTA112SM functions as a 7-port IEEE 1149.1 multidrop multiplexer that enables hierarchical test bus management. It allows a single test controller to selectively access individual or grouped local scan chains across multiple boards or devices via addressable backplane communication. Its design eliminates the need for flat, serial scan chains - improving test throughput, fault isolation, and system-level programming efficiency in complex embedded systems.
Does the SCANSTA112SM support hot-swap or live insertion in backplane systems?
Yes, the SCANSTA112SM is explicitly qualified for live insertion/withdrawal per its datasheet. Key enablers include its known power-up state, OE-controlled TRI-STATE outputs on all local scan ports, robust ESD handling (2500V HBM), and backplane I/O structures designed for capacitive-load-safe behavior during power-off conditions. These features prevent bus contention and ensure reliable reconnection without system reset.
How does the SCANSTA112SM handle TRST signals across its 7 local scan ports?
The SCANSTA112SM provides independent TRST(01–06) outputs for six local ports and uses TLR_TRST/TLR_TRST6 pins to control TRST0–TRST5 and TRST6 separately. This allows selective asynchronous reset of individual TAP controllers (e.g., resetting only an FPGA while leaving an adjacent ASIC active), preserving test context and enabling targeted device recovery without disrupting the entire scan network.
What are the key differences between ScanBridge Mode and Stitcher Mode on the SCANSTA112SM?
ScanBridge Mode requires two-stage protocol execution: Level-1 to address/select the SCANSTA112SM via S0–S7, then Level-2 to configure LSPsel0–6 for port inclusion. Stitcher Mode bypasses both levels using SB/S and TRANS pins, directly enabling operational mode - reducing setup overhead and accelerating FPGA configuration or debug sessions where fixed port mapping is acceptable.
Can the SCANSTA112SM be used to route non-JTAG signals such as flash programming pulses?
Yes, the SCANSTA112SM includes general-purpose pass-through I/O: A0B0/A1B0 inputs and Y0B0/Y1B0 outputs (plus A001/A101/Y001/Y101 on LSP0/LSP1) support routing of auxiliary signals. These are commonly used to deliver precise write-enable pulses to NOR/NAND flash or monitor ready/busy status - extending its role beyond pure JTAG to mixed-signal board-level control and diagnostics.
SCANSTA112SM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 100-LFBGA
- Packaging:
- Tray
- Product Status:
- Not For New Designs
- Applications:
- Testing Equipment
- Interface:
- IEEE 1149.1
- Voltage - Supply:
- 3V ~ 3.6V
- Supplier Device Package:
- 100-FBGA (10x10)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
SCANSTA112SM FAQ
1.How can I place an order for SCANSTA112SM through Aetrix?
Please submit a Request for Quotation (RFQ) for SCANSTA112SM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SCANSTA112SM reliable?
The price and inventory of SCANSTA112SM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SCANSTA112SM is usually 5 days.
3.What payment methods are accepted for SCANSTA112SM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SCANSTA112SM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SCANSTA112SM?
SCANSTA112SM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SCANSTA112SM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SCANSTA112SM?
For technical support, including SCANSTA112SM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SCANSTA112SM requirements.
6.How does Aetrix verify that SCANSTA112SM is sourced from the original manufacturer or authorized distributors?
All SCANSTA112SM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SCANSTA112SM meets industry standards.
7.What is the process for return or replacement of SCANSTA112SM?
All SCANSTA112SM units undergo pre-shipment inspection (PSI). If there is an issue with SCANSTA112SM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SCANSTA112SM part is unused and in its original packaging.
Return procedure for SCANSTA112SM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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