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NXP Semiconductors SCC2681AC1N28,112
- Part No.:
- SCC2681AC1N28,112
- Manufacturer:
- NXP Semiconductors
- Package:
- 28-DIP (0.600", 15.24mm)
- Datasheet:
-
SCC2681AC1N28,112.pdf
- Description:
- IC UART 28-DIP
- Quantity:
- Payment:
- Shipping:
Inventory:1,759
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Product details
Overview
SCC2681AC1N28 from NXP Semiconductors (formerly Philips) is a dual-channel CMOS asynchronous receiver/transmitter (DUART) in a 28-pin DIP package, supporting independent full-duplex serial communication at up to 115.2 kbaud per channel, with quadruple receiver buffering and programmable data formats (5–8 data bits, 1/1.5/2 stop bits, odd/even/no parity), used in industrial terminal systems and legacy embedded controllers requiring RS-232/422 interface expansion.
For engineers reviewing the SCC2681AC1N28 datasheet, SCC2681AC1N28 pinout, SCC2681AC1N28 application, or SCC2681AC1N28 equivalent, key selection considerations include its 28-pin DIP footprint, independent baud rate programming per channel (18 fixed rates + external clock options), on-chip crystal oscillator (3.6864 MHz), 5 V single-supply operation, and interrupt-driven or polled I/O support with maskable status conditions.
Technical Context
The SCC2681AC1N28 integrates two independent UART channels sharing a common 8-bit bidirectional data bus (D0–D7), address decoding (A0–A3), and chip enable (CEN) logic. Each channel features separate receiver and transmitter baud rate generators selectable from 18 fixed rates (50–115.2 kbaud), a 16× clock derived from an internal counter/timer, or external 1×/16× clock inputs via IP3–IP6 pins.
It implements a unified interrupt architecture with a single active-low open-drain INTRN output and eight maskable sources-including RxRDY/TxRDY, framing/parity errors, break detection, and input port change-plus configurable discrete interrupt outputs on OP3–OP7. The device includes a 7-bit input port (IP0–IP6) with change-of-state detection and an 8-bit output port (OP0–OP7) supporting individual bit set/reset and functional assignment (e.g., RTS, Tx/Rx clocks, DMA signals).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Channels | Dual independent full-duplex UARTs (Channel A and Channel B) |
| Max Baud Rate | 115.2 kbaud per channel using internal 18-rate generator or external clock |
| Data Format | Programmable: 5–8 data bits, odd/even/no/force parity, 1/1.5/2 stop bits in 1/16-bit increments |
| Receiver Buffering | Quadruple-buffered RHR to prevent overrun and reduce interrupt overhead |
| Supply Voltage | +5 V ± 5% (commercial grade); operates over 0 °C to +70 °C ambient |
| Package | 28-pin plastic DIP (600 mil width), SOT117-1 footprint |
| Crystal Oscillator | On-chip oscillator supporting 3.6864 MHz crystal across X1/CLK and X2 pins |
| Interrupt Architecture | Single INTRN output with 8 maskable sources; OP3–OP7 configurable as discrete wire-ORable interrupts |
Pinout & Package
SCC2681AC1N28 uses a 28-pin plastic dual in-line package (DIP), 600 mil width, SOT117-1. Pin 1 is index corner; pins 1, 12, 23, and 34 are not connected. Power is applied at pin 28 (VCC) and pin 14 (GND). The device supports microprocessor bus interfacing via 8-bit bidirectional data bus (D0–D7), 4-bit address bus (A0–A3), and control signals (CEN, WRN, RDN, RESET).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 12, 23, 34 | NC | No connection - must remain unconnected per datasheet |
| 2–4, 6–7 | A0–A3 | Address inputs selecting internal registers (MR, SR, CR, etc.) for read/write access |
| 5–6, 8, 40, 41–43 | IP0–IP6 | 7-bit multipurpose input port; configurable as CTS, clock inputs, or change-of-state monitored signals |
| 9 | WRN | Active-low write strobe - initiates register write on rising edge when CEN is low |
| 10 | RDN | Active-low read strobe - presents register contents on D0–D7 on falling edge when CEN is low |
| 11, 13 | RXDB, TXDB | Channel B serial I/O - receiver input (RxDB) and transmitter output (TxDB), mark=HIGH, space=LOW |
| 14 | GND | Ground reference for all digital and analog circuitry |
| 15 | INTRN | Active-low open-drain interrupt output - asserts when any of eight maskable conditions occur |
| 16–17, 29–32 | OP0–OP7 | 8-bit multipurpose output port - individually set/reset; assignable to RTS, Tx/Rx clocks, or interrupt signals |
| 18–21, 25–27 | D0–D7 | Bidirectional 3-state data bus - transfers commands, data, and status between CPU and DUART |
| 22 | X2 | Crystal oscillator second terminal - left unconnected if external clock used on X1/CLK |
| 23 | X1/CLK | Crystal or external clock input - accepts 1.0–4.0 MHz signal; powers baud rate generator and timer |
| 24 | RXDA | Channel A receiver serial input - least significant bit first; "mark" = HIGH, "space" = LOW |
| 25 | RESET | Active-high reset - clears registers, stops timer, disables transmitters, sets OP0–OP7 HIGH |
| 26 | CEN | Active-low chip enable - enables D0–D7 bus and controls WRN/RDN sensitivity |
| 28 | VCC | +5 V power supply - requires local decoupling capacitor per layout guidelines |
| 33, 35 | TXDA, RXDA | Channel A serial I/O - transmitter output (TxDA) and receiver input (RxDA), same voltage convention as Channel B |
Key Features
| Feature | Design Value |
|---|---|
| Independent baud rate per channel | Each receiver and transmitter selects from 18 fixed rates, counter/timer-derived rate, or external 1×/16× clock - enables dual-speed operation (e.g., host-to-terminal and terminal-to-peripheral links) |
| Quadruple receiver buffering | Four-level receive holding register reduces CPU polling frequency and prevents character loss during high-throughput or interrupt-latency scenarios |
| Programmable flow control | Remote transmitter disable via FFULL status and OP4/OP5 interrupt generation - supports hardware handshaking without external logic |
| Multi-function I/O ports | 7-bit input port with change-of-state detection on IP0–IP3 and 8-bit output port with individual bit set/reset - replaces discrete GPIO expanders in legacy designs |
| Auto 485 turn-around | OP0–OP1 configurable as RTS outputs with automatic deactivation after transmission - eliminates need for external direction-control logic in half-duplex RS-485 systems |
| Start-end break detection | Identifies break conditions originating mid-character and generates dedicated interrupt - critical for multidrop line discipline and wake-up signaling |
Applications
| Industrial Terminal Systems | Legacy Embedded Controllers |
|---|---|
Use Scenario: Clustered intelligent terminals communicating with a central host over RS-232/422 links, requiring asymmetric speed negotiation (e.g., 9600 bps upstream, 38.4 kbps downstream). IC Role / Device Role / Timing Role: SCC2681AC1N28 serves as dual-channel serial interface controller, managing independent baud rates, receiver buffering, and RTS/CTS handshaking per channel. Use Value: Eliminates need for two discrete UARTs and external glue logic; quadruple buffering ensures no character loss during burst traffic from multiple peripherals. | Use Scenario: Retrofitting aging PLCs or CNC machines with additional serial ports while preserving existing 28-pin DIP PCB footprints and 5 V logic levels. IC Role / Device Role / Timing Role: SCC2681AC1N28 acts as drop-in serial expansion IC, providing two full-duplex channels with on-chip oscillator and compatible timing margins. Use Value: Maintains board compatibility without redesign; built-in crystal oscillator removes external timing components and simplifies BOM. |
| Point-of-Sale (POS) Peripherals | Medical Device Data Loggers |
Use Scenario: Integrating barcode scanners, receipt printers, and magnetic stripe readers into a single POS terminal chassis with isolated serial interfaces. IC Role / Device Role / Timing Role: SCC2681AC1N28 functions as centralized serial hub, assigning OP0–OP1 as RTS outputs and OP4–OP5 as RxRDY interrupts for each peripheral. Use Value: Reduces component count by consolidating handshaking and status signaling onto one IC; auto 485 turn-around supports future RS-485 printer upgrades. | Use Scenario: Continuous acquisition of sensor data (ECG, SpO₂) transmitted via RS-232 to external storage or telemetry modules in battery-powered portable devices. IC Role / Device Role / Timing Role: SCC2681AC1N28 operates in low-power polled mode with wake-up break detection, managing data flow from two independent analog front-end subsystems. Use Value: Start-end break interrupt enables reliable sleep/wake coordination; quadruple buffering accommodates variable sensor sampling intervals without CPU intervention. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual UART applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SCC2692AC1N28 | Same pinout and register map; adds FIFO buffers (16-byte depth per channel) and enhanced interrupt masking | Higher throughput and lower CPU load in interrupt-driven systems; requires minor firmware update for FIFO control | Select when upgrading legacy SCC2681AC1N28 designs needing higher serial bandwidth or reduced ISR overhead |
| TL16C550CP | 28-pin DIP, 16-byte FIFO, 5 V operation; lacks on-chip oscillator, requires external clock; different register layout and interrupt handling | Widely supported in PC BIOS and DOS drivers; no crystal support limits self-contained timing | Choose for PC-compatible embedded systems where software reuse and driver availability outweigh oscillator integration benefits |
Compared with SCC2681AC1N28, SCC2692AC1N28 delivers higher buffer depth and backward-compatible control, while TL16C550CP offers broader software ecosystem support at the cost of external timing components and non-drop-in register programming.
Availability
SCC2681AC1N28 is available at Aetrix Electronics and suitable for industrial terminal systems, legacy embedded controllers, point-of-sale peripherals, and medical device data loggers requiring stable component supply and long-term obsolescence management.
Supply support for SCC2681AC1N28 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company formed from the spin-off of Philips' semiconductor division, specializing in secure connectivity, automotive, industrial, and IoT solutions with strong legacy IP in communications ICs.
The SCC2681AC1N28 belongs to NXP's legacy communications interface product line, designed specifically for robust, low-power dual-channel serial expansion in industrial and embedded systems requiring pin-compatible upgrade paths and long-lifecycle support.
FAQ
What is the maximum operating temperature range for the SCC2681AC1N28?
The SCC2681AC1N28 is rated for commercial operation from 0 °C to +70 °C ambient temperature. Its supply voltage tolerance is +5 V ± 5%. This specification is defined in the Ordering Information table of the official datasheet and applies specifically to the 'AC' suffix variant. Industrial-grade alternatives (e.g., SCC2681AE1N28) extend the range to –40 °C to +85 °C but require verification of voltage tolerance (±10%) and qualification testing for target applications.
Does the SCC2681AC1N28 support RS-485 half-duplex operation out of the box?
Yes, the SCC2681AC1N28 supports RS-485 half-duplex operation through its OP0 and OP1 outputs, which can be configured as automatic RTS signals with turn-around timing. When enabled, these outputs deactivate one bit time after transmission completes, eliminating the need for external direction-control logic. This capability is documented in the Output Port section of the datasheet and requires proper configuration of the OPCR and channel mode registers - no external components are needed for basic auto-turnaround functionality.
Can the SCC2681AC1N28 generate baud rates not listed in the standard 18-rate table?
Yes, the SCC2681AC1N28 can generate non-standard baud rates using its 16-bit programmable counter/timer. By loading custom divisor values into the CTUR/CTLR registers, users can derive precise rates up to 115.2 kbaud - including those not in the fixed table (e.g., 125 kbaud, 250 kbaud). This method is explicitly supported in the Timing Circuits section and requires configuring the clock selector to use the counter/timer output instead of the fixed-rate generator.
How does the quadruple receiver buffering in the SCC2681AC1N28 improve system reliability?
The quadruple receiver buffering in the SCC2681AC1N28 provides four levels of receive holding register (RHR) depth per channel, significantly reducing the risk of receiver overrun during high-speed or burst serial traffic. This allows the host CPU more time to service interrupts or poll status before new characters arrive - especially valuable in systems with variable interrupt latency or limited processing bandwidth. The feature is implemented in hardware and requires no additional configuration beyond enabling the receiver.
Is an external crystal required for the SCC2681AC1N28 to function?
No, an external crystal is not strictly required for the SCC2681AC1N28 to function. While it includes an on-chip crystal oscillator designed for a 3.6864 MHz crystal across X1/CLK and X2, the device also accepts an external clock signal (1.0–4.0 MHz) applied directly to the X1/CLK pin. In that case, X2 should remain unconnected. Both configurations are fully supported and validated in the Clock Timing section of the datasheet, giving designers flexibility in timing source selection.
SCC2681AC1N28,112 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 28-DIP (0.600", 15.24mm)
- Series:
- -
- Packaging:
- Tube
- Product Status:
- Obsolete
- Features:
- Configurable GPIO, Internal Oscillator, Timer/Counter
- Number of Channels:
- 2, DUART
- FIFO's:
- -
- Protocol:
- -
- Data Rate (Max):
- 1Mbps
- Voltage - Supply:
- 5V
- With Auto Flow Control:
- Yes
- With IrDA Encoder/Decoder:
- -
- With False Start Bit Detection:
- Yes
- With Modem Control:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 28-DIP
SCC2681AC1N28,112 FAQ
1.How can I place an order for SCC2681AC1N28,112 through Aetrix?
Please submit a Request for Quotation (RFQ) for SCC2681AC1N28,112 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SCC2681AC1N28,112 reliable?
The price and inventory of SCC2681AC1N28,112 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SCC2681AC1N28,112 is usually 5 days.
3.What payment methods are accepted for SCC2681AC1N28,112?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SCC2681AC1N28,112 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SCC2681AC1N28,112?
SCC2681AC1N28,112 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SCC2681AC1N28,112 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SCC2681AC1N28,112?
For technical support, including SCC2681AC1N28,112 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SCC2681AC1N28,112 requirements.
6.How does Aetrix verify that SCC2681AC1N28,112 is sourced from the original manufacturer or authorized distributors?
All SCC2681AC1N28,112 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SCC2681AC1N28,112 meets industry standards.
7.What is the process for return or replacement of SCC2681AC1N28,112?
All SCC2681AC1N28,112 units undergo pre-shipment inspection (PSI). If there is an issue with SCC2681AC1N28,112, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SCC2681AC1N28,112 part is unused and in its original packaging.
Return procedure for SCC2681AC1N28,112:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SCC2681AC1N28,112 Tags
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SC16IS741AIPWJ
NXP Semiconductors
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