NXP Semiconductors SCC2681TC1A44,529
- Part No.:
- SCC2681TC1A44,529
- Manufacturer:
- NXP Semiconductors
- Package:
- 44-LCC (J-Lead)
- Datasheet:
-
SCC2681TC1A44,529.pdf
- Description:
- IC DUART 1MBPS 44PLCC
- Quantity:
- Payment:

- Shipping:

Inventory:1,053
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Product details
Overview
SCC2681TC1A44 from NXP Semiconductors (formerly Philips Semiconductors) is a dual-channel CMOS universal asynchronous receiver/transmitter (DUART) in 44-pin PLCC package, supporting independent full-duplex serial communication on two channels with programmable baud rates up to 115.2 kbaud, quadruple receiver buffering, and +5 V single-supply operation for industrial embedded control systems.
For engineers reviewing the SCC2681TC1A44 datasheet, SCC2681TC1A44 pinout, SCC2681TC1A44 application, or SCC2681TC1A44 equivalent, key selection considerations include its 44-pin PLCC footprint, dual-channel interrupt-driven I/O capability, 16-bit counter/timer, multipurpose I/O ports, and compatibility with legacy microprocessor buses requiring minimal wait states.
Technical Context
The SCC2681TC1A44 implements two independent UART channels sharing a common 8-bit bidirectional data bus, address decoding (A0–A3), and control signals (RDN, WRN, CEN). Each channel features separate receiver and transmitter shift registers, holding registers, status registers, and mode registers, enabling simultaneous asynchronous serial communication at different data formats and baud rates.
Its timing architecture integrates an on-chip crystal oscillator (X1/CLK, X2), external clock inputs for Rx/Tx (IP4–IP6, IP3, IP5), and a 16-bit programmable counter/timer used for baud rate generation or general-purpose timing. The device supports automatic echo, local/remote loopback, false start bit detection, line break handling, and multidrop wake-up mode via dedicated control logic and status flags.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Baud Rate Range | 50 to 115.2 kbaud (18 fixed rates); non-standard rates supported via 16-bit counter/timer or external 1×/16× clocks |
| Data Format | 5–8 data bits, odd/even/no/force parity, 1/1.5/2 stop bits programmable in 1/16-bit increments per channel |
| Receiver Buffering | Quadruple-buffered receive holding registers per channel reduce interrupt overhead and prevent overrun in high-speed polling |
| Bus Interface | 8-bit parallel microprocessor interface with CEN/RDN/WRN control; fast bus cycle eliminates wait states with CPUs ≥8 MHz |
| Supply & Temp | +5 V ±10% supply; commercial temperature range 0 °C to +70 °C; CMOS process ensures low power consumption (~10 mA typical ICC) |
| Interrupt System | Single active-low open-drain INTRN output with eight maskable sources; optional wire-ORable outputs OP3–OP7 for discrete interrupts |
| I/O Ports | 7-bit input port (IP0–IP6) with change-of-state detection and pull-ups; 8-bit output port (OP0–OP7) with individual bit set/reset and auto RS-485 turn-around |
Pinout & Package
SCC2681TC1A44 is housed in a 44-pin plastic leaded chip carrier (PLCC, SOT187-2) with J-lead configuration, designed for surface-mount assembly and thermal reliability in industrial PCB environments.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| D0–D7 (Pins 18–28) | Bidirectional Data Bus | Transfers commands, data, and status between CPU and DUART; D0 = LSB; three-state when CEN HIGH |
| CEN (Pin 39) | Chip Enable | Active-LOW enable for all bus operations; places D0–D7 in high-impedance state when HIGH |
| RDN (Pin 10), WRN (Pin 9) | Read/Write Strobes | Edge-triggered controls: RDN falling edge initiates read; WRN rising edge latches write data |
| A0–A3 (Pins 2,4,6,7) | Register Address Inputs | Select internal registers (e.g., CSR, IMR, OPR) and ports; decode 16 addresses including channel A/B control/status |
| RxDA (Pin 35), RxDB (Pin 11) | Serial Input Channels | Asynchronous receive inputs for Channel A and B; sampled on rising edge of Rx clock (internal or external) |
| TxDA (Pin 33), TxDB (Pin 13) | Serial Output Channels | Transmit outputs for Channel A and B; driven LOW for 'space', HIGH for 'mark'; held in mark state when idle |
| OP0–OP7 (Pins 14,15,16,17,29,30,31,32) | Multipurpose Outputs | Configurable as RTS/CTS signals, Tx/Rx clock outputs, or interrupt flags (e.g., OP4 = RxRDYA/FFULLA) |
| IP0–IP6 (Pins 3,5,8,40,41,42,43) | Multipurpose Inputs | Support CTS, external Tx/Rx clocks, counter/timer clock, or general-purpose inputs with 100 kΩ pull-ups |
| X1/CLK (Pin 36), X2 (Pin 37) | Clock Oscillator Terminals | Connect 2–4 MHz crystal (e.g., 3.6864 MHz) for on-chip oscillator; X2 left unconnected if external clock used |
| INTRN (Pin 24) | Interrupt Request | Active-LOW open-drain output signaling any enabled interrupt condition (e.g., RxRDY, TxRDY, break, overrun) |
| RESET (Pin 38) | Hardware Reset | Active-HIGH signal clearing all registers, stopping timer, disabling transmitters, and setting default modes |
| VCC (Pin 44), GND (Pin 22) | Power Supply | +5 V ±10% supply and ground reference; decoupling recommended near pins for noise immunity |
Key Features
| Feature | Design Value |
|---|---|
| Fast bus cycle time | Eliminates CPU wait states with processors ≥8 MHz, enabling high-throughput I/O in real-time embedded systems |
| Independent channel programming | Each UART channel supports unique data format, baud rate, and mode (normal, echo, loopback), enabling dual-speed terminal clusters |
| Quadruple receiver buffering | Reduces interrupt frequency by 4× versus single-buffer designs, lowering CPU load in interrupt-driven communication stacks |
| Auto RS-485 turn-around | OP0–OP7 output port includes hardware-controlled direction switching for half-duplex RS-485 without external logic |
| Flow control & error detection | Hardware-enforced RTS/CTS handshake plus parity/framing/overrun/false-start/break detection ensures robust serial link integrity |
| Multidrop wake-up mode | Enables selective activation of remote stations via break detection and address matching, reducing power in distributed networks |
Applications
| Industrial PLC Communication | Legacy Terminal Emulation |
|---|---|
|
Use Scenario: Connecting programmable logic controllers to HMI panels and remote I/O modules via RS-232/RS-485 links. IC Role / Device Role / Timing Role: Dual-channel DUART handles simultaneous master-slave polling and diagnostic messaging while managing flow control and break detection. Use Value: Quadruple buffering prevents data loss during high-cycle scan times; auto RS-485 turn-around simplifies hardware design and reduces component count. |
Use Scenario: Emulating VT100/ANSI terminals in embedded systems using legacy ASCII-based protocols. IC Role / Device Role / Timing Role: SCC2681TC1A44 provides two independent serial ports for keyboard input and display output with configurable parity and stop bits. Use Value: Independent baud rate selection per channel allows mismatched host/peripheral speeds; local loopback mode enables self-test without external cabling. |
| Point-of-Sale (POS) Systems | Medical Device Serial Interfaces |
|
Use Scenario: Interfacing receipt printers, barcode scanners, and cash drawers in retail POS terminals. IC Role / Device Role / Timing Role: Acts as central serial hub managing multiple peripherals with distinct timing requirements and handshaking protocols. Use Value: Multipurpose I/O ports (IP0–IP6, OP0–OP7) replace discrete logic for printer busy sensing and drawer trigger control. |
Use Scenario: Enabling serial diagnostics and firmware updates in FDA-class II medical instruments with strict EMI and reliability requirements. IC Role / Device Role / Timing Role: Provides isolated, error-checked UART channels for service port access and internal subsystem telemetry. Use Value: On-chip crystal oscillator eliminates external timing components; false start bit and break detection improve protocol robustness in noisy clinical environments. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual UART applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SCC2692BZ | Same pinout and register compatibility; enhanced ESD protection (±4 kV HBM), wider temp range (–40 °C to +85 °C), improved AC timing margins | Preferred for extended-temperature industrial deployments where long-term reliability under thermal cycling is critical | Select SCC2692BZ when operating beyond 0–70 °C or requiring higher ESD immunity without redesign |
| TL16C550CP | Different pinout (48-pin TQFP); FIFO-based (16-byte buffers vs. quadruple); no integrated counter/timer or multidrop wake-up | Suitable for PC-compatible UART replacement but lacks SCC2681TC1A44's I/O port flexibility and dual-speed channel independence | Choose TL16C550CP only when migrating from PC-style ISA bus systems with existing FIFO-aware drivers |
Compared with SCC2681TC1A44, SCC2692BZ offers drop-in thermal and ESD upgrades while preserving software and layout; TL16C550CP trades I/O versatility and dual-channel autonomy for deeper FIFO buffering and x86 BIOS compatibility - neither matches the SCC2681TC1A44's integrated counter/timer, auto RS-485, or multidrop wake-up capabilities.
Availability
SCC2681TC1A44 is available at Aetrix Electronics and suitable for industrial automation, legacy terminal interfacing, and point-of-sale systems requiring stable component supply, long-lifecycle support, and proven interoperability with 8/16-bit microprocessors.
Supply support for SCC2681TC1A44 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors (formerly Philips Semiconductors) is a global leader in high-performance mixed-signal ICs, with expertise in connectivity, security, and automotive electronics.
The SCC2681 product line was developed for industrial and embedded communications, delivering robust dual UART functionality with integrated timing, I/O, and protocol features for resource-constrained microcontroller systems.
FAQ
What is the maximum baud rate supported by the SCC2681TC1A44?
The SCC2681TC1A44 supports standard baud rates up to 115.2 kbaud using its internal 16-bit counter/timer or external clock inputs. With a 3.6864 MHz crystal, it achieves precise 115.2 kbaud (16× oversampling). Non-standard rates are possible up to 115.2 kbaud via programmable divisor values, and external 1× or 16× clocks allow further flexibility. The SCC2681TC1A44 does not support rates above 115.2 kbaud in standard configurations.
Does the SCC2681TC1A44 support RS-485 half-duplex operation?
Yes, the SCC2681TC1A44 supports RS-485 half-duplex operation through its multipurpose output port. OP0–OP7 can be configured for automatic direction control: when enabled, the DUART asserts a transmit-enable signal synchronized with TxDA/TxDB activity, eliminating need for external transceiver control logic. This auto turn-around feature is programmable per channel and is documented in the SCC2681TC1A44 OPCR register settings.
Can both UART channels of the SCC2681TC1A44 operate at different baud rates simultaneously?
Yes, the SCC2681TC1A44 allows independent baud rate configuration for each channel. Each receiver and transmitter can select from 22 fixed rates, non-standard rates derived from the shared 16-bit counter/timer, or external 1×/16× clocks. This enables true dual-speed operation - for example, Channel A at 9600 baud for a modem and Channel B at 115.2 kbaud for a printer - without timing conflict or software overhead.
What is the function of the IP0–IP6 and OP0–OP7 pins on the SCC2681TC1A44?
IP0–IP6 (7-bit input port) and OP0–OP7 (8-bit output port) are programmable multifunction I/O resources. IP pins support clear-to-send inputs, external clock sources, or general-purpose sensing with change-of-state detection and internal pull-ups. OP pins serve as request-to-send outputs, clock outputs, interrupt flags (e.g., OP4 = RxRDYA), or general-purpose control signals with individual bit set/reset. Their functions are selected via OPCR and IPCR registers in the SCC2681TC1A44.
Is the SCC2681TC1A44 compatible with modern microcontrollers using 3.3 V I/O?
No, the SCC2681TC1A44 is a +5 V-only device with TTL/CMOS input thresholds (VIH = 2.0 V min, VIL = 0.8 V max) and output drive levels referenced to VCC = +5 V. Direct connection to 3.3 V microcontrollers risks overvoltage damage to inputs and logic-level incompatibility on outputs. Level-shifting circuitry (e.g., TXB0108 or discrete MOSFET translators) is required for safe interfacing with 3.3 V systems. The SCC2681TC1A44 datasheet specifies no 3.3 V operation.
SCC2681TC1A44,529 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 44-LCC (J-Lead)
- Series:
- -
- Packaging:
- Tube
- Product Status:
- Obsolete
- Features:
- Configurable GPIO, Internal Oscillator, Timer/Counter
- Number of Channels:
- 2, DUART
- FIFO's:
- -
- Protocol:
- -
- Data Rate (Max):
- 1Mbps
- Voltage - Supply:
- 5V
- With Auto Flow Control:
- Yes
- With IrDA Encoder/Decoder:
- -
- With False Start Bit Detection:
- Yes
- With Modem Control:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 44-PLCC (16.59x16.59)
SCC2681TC1A44,529 FAQ
1.How can I place an order for SCC2681TC1A44,529 through Aetrix?
Please submit a Request for Quotation (RFQ) for SCC2681TC1A44,529 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SCC2681TC1A44,529 reliable?
The price and inventory of SCC2681TC1A44,529 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SCC2681TC1A44,529 is usually 5 days.
3.What payment methods are accepted for SCC2681TC1A44,529?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SCC2681TC1A44,529 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SCC2681TC1A44,529?
SCC2681TC1A44,529 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SCC2681TC1A44,529 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SCC2681TC1A44,529?
For technical support, including SCC2681TC1A44,529 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SCC2681TC1A44,529 requirements.
6.How does Aetrix verify that SCC2681TC1A44,529 is sourced from the original manufacturer or authorized distributors?
All SCC2681TC1A44,529 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SCC2681TC1A44,529 meets industry standards.
7.What is the process for return or replacement of SCC2681TC1A44,529?
All SCC2681TC1A44,529 units undergo pre-shipment inspection (PSI). If there is an issue with SCC2681TC1A44,529, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SCC2681TC1A44,529 part is unused and in its original packaging.
Return procedure for SCC2681TC1A44,529:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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