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NXP Semiconductors SCC2691AC1A28,512
- Part No.:
- SCC2691AC1A28,512
- Manufacturer:
- NXP Semiconductors
- Package:
- 28-LCC (J-Lead)
- Datasheet:
-
SCC2691AC1A28,512.pdf
- Description:
- IC UART CMOS LSI 28PLCC
- Quantity:
- Payment:
- Shipping:
Inventory:2,363
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Product details
Overview
SCC2691AC1A28,512 from NXP Semiconductors (formerly Philips Semiconductors) is a CMOS-LSI universal asynchronous receiver/transmitter (UART) with full-duplex serial communication capability, quadruple-buffered receiver FIFO, independent receiver/transmitter baud rate selection (up to 115.2 kbaud), and integrated 16-bit counter/timer. It operates from a single +5 V supply and supports industrial temperature range (–40°C to +85°C) in PLCC-28 package.
For engineers reviewing the SCC2691AC1A28,512 datasheet, SCC2691AC1A28,512 pinout, SCC2691AC1A28,512 application, or SCC2691AC1A28,512 equivalent, key selection considerations include dual-speed channel support, programmable data format (5–8 bits, parity options, 1/1.5/2 stop bits), false start bit detection, line break handling, and power-down mode reducing current to 0.5 µA.
Technical Context
The SCC2691AC1A28,512 implements a fully programmable UART core with independent clock selectors for receiver and transmitter paths, enabling asymmetric baud rates-e.g., 9600 bps receive / 19200 bps transmit-critical for clustered terminal systems. Its timing architecture integrates an on-chip crystal oscillator (3.6864 MHz nominal), 18 fixed-rate baud generator, and 16-bit counter/timer usable as 1X/16X clock source or event timer.
Receiver operation includes quadruple buffering (3-character FIFO + shift register), automatic RTS flow control via MPI/MPO handshaking, and status-stamped character reception (parity/framing/overrun/break). Transmitter supports break generation, local/remote loopback, and automatic echo modes-all configurable via mode registers MR1/MR2 and auxiliary control register ACR.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Baud Rate Range | 50 to 115.2 kbaud; supports non-standard user-defined rates via 16-bit counter/timer. |
| Data Format | 5–8 data bits, odd/even/no/force parity, 1/1.5/2 stop bits programmable in 1/16-bit increments. |
| Receiver Buffering | Quadruple buffered: 3-character FIFO + 1-shift-register stage; reduces interrupt overhead and overrun risk. |
| Power Supply | +5 V ±10%; active current ≤2.5 mA (industrial temp), power-down current ≤0.5 µA. |
| Operating Temperature | –40°C to +85°C (industrial grade); validated per ordering code SCC2691AE1A28. |
| Interrupt Capability | Single open-drain INTRN output with seven maskable sources: TxRDY, RxRDY/FFULL, break, MPI change, C/T terminal count, etc. |
| Package | 28-pin Plastic Leaded Chip Carrier (PLCC); lead-free compatible per SOT261-2 footprint. |
Pinout & Package
SCC2691AC1A28,512 is housed in a 28-pin PLCC (SOT261-2) package with J-lead geometry, 1.27 mm pitch, and body size 11.5 × 11.5 mm. Pin 1 is located at the index corner adjacent to the notch.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| D0–D7 | Data Bus I/O | 8-bit bidirectional TTL-compatible bus; transfers registers, commands, and status under CEN/WRN/RDN control. |
| CEN | Chip Enable Input | Active-low enable for CPU interface; places D-bus in high-impedance state when deasserted. |
| WRN | Write Strobe Input | Active-low write trigger; latches data on falling edge when CEN is low. |
| RDN | Read Strobe Input | Active-low read trigger; places selected register contents on D-bus on falling edge when CEN is low. |
| A0–A2 | Address Inputs | 3-bit address selects one of eight register groups (MR1/MR2, SR/CSR, RHR/THR, ISR/IMR, CTU/CTUR, CTL/CTLR, ACR, CR). |
| RESET | Master Reset Input | Active-high reset clears SR, IMR, ISR, sets MR pointer to MR1, disables Tx/Rx, forces TxD high. |
| INTRN | Interrupt Request Output | Open-drain active-low interrupt; requires external pull-up; asserts on any enabled interrupt condition. |
| X1/CLK | Clock Input | Accepts 3.6864 MHz crystal or external clock (0–4 MHz); drives internal oscillator, BRG, and C/T. |
| X2 | Clock Input | Crystal second terminal; left unconnected or grounded if external clock used. |
| RxD | Receiver Input | Asynchronous serial input sampled at 1X or 16X clock; supports false start bit rejection and break detection. |
| TxD | Transmitter Output | Asynchronous serial output; idle high; supports break generation and auto-echo mode. |
| MPO | Multi-Purpose Output | Programmable function: RTSN, C/T output, Tx/Rx 1X/16X clocks, TxRDY, or RxRDY/FFULL. |
| MPI | Multi-Purpose Input | Configurable as CTSN, CTCLK, RTCLK, or GPI; internal VCC pull-up (1–4 µA). |
| VCC | Power Supply | +5 V ±10% supply; powers all internal logic and I/O buffers. |
| GND | Ground Reference | Signal and power ground reference for all internal circuits and I/O pins. |
Key Features
| Feature | Design Value |
|---|---|
| Independent Rx/Tx Baud Rate Selection | Enables dual-speed channel operation (e.g., host-to-terminal and terminal-to-host at different rates) without external clock switching logic. |
| Quadruple-Buffered Receiver | 3-deep FIFO + shift register minimizes CPU interrupt frequency and prevents overrun in burst-receive scenarios. |
| Programmable Flow Control | MPO-configurable RTSN automatically deasserts when FIFO fills and reasserts on space availability-enabling hardware handshaking with remote UARTs. |
| Low-Power Mode | Freezes oscillator while preserving register contents; reduces ICC from 2.5 mA to ≤0.5 µA-ideal for battery-backed or sleep-mode embedded systems. |
| Multi-Function Counter/Timer | 16-bit down-counter/timer with eight selectable clock sources and MPO output routing-replaces discrete timing ICs in system control applications. |
| Address Recognition Mode | Supports multi-processor wake-up via address/data bit framing; allows selective receiver activation in shared-bus networks without continuous polling. |
Applications
| Industrial HMI Terminals | Legacy Equipment Serial Gateways |
|---|---|
|
Use Scenario: Connecting PLCs, HMIs, and panel PCs via RS-232/RS-422 interfaces in factory automation cabinets where space and thermal constraints limit component count. IC Role / Device Role / Timing Role: UART interface bridging microcontroller UART peripherals to external serial devices; provides robust framing, break detection, and hardware flow control. Use Value: Quadruple buffering and RTS-driven handshaking prevent data loss during high-throughput SCADA polling cycles; industrial temperature rating ensures reliability in uncooled enclosures. |
Use Scenario: Retrofitting legacy CNC machines, barcode scanners, or point-of-sale terminals with modern microcontrollers lacking native UART peripherals or requiring extended baud rate flexibility. IC Role / Device Role / Timing Role: Standalone UART co-processor handling serial protocol framing, parity generation/checking, and clock domain translation between MCU and peripheral. Use Value: Independent Rx/Tx clock selection enables interoperability with legacy devices operating at non-standard rates (e.g., 75 bps uplink / 19.2 kbps downlink). |
| Multi-Processor Communication Nodes | Embedded Modem Control Interfaces |
|
Use Scenario: Distributed sensor networks using master-slave topology over shared RS-485 bus, where only addressed nodes process traffic to reduce bus contention and power consumption. IC Role / Device Role / Timing Role: Address recognition UART enabling selective wake-up; receiver disabled until address frame matches node ID. Use Value: Reduces average system current by >90% versus continuously listening UARTs; eliminates need for external address decoding logic. |
Use Scenario: Integrating dial-up or cellular modems into embedded gateways where AT command parsing, line break signaling, and modem status monitoring require precise serial timing control. IC Role / Device Role / Timing Role: Primary UART managing modem control lines (RTS/CTS), detecting line breaks, and generating clean break signals for modem hangup/reset. Use Value: On-chip break generation and detection eliminate software-timed GPIO toggling; false start bit rejection improves AT command reliability over noisy PSTN lines. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar UART applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SCC2692AC1A28 | Dual-channel version; identical pinout and register map; second UART channel shares clock and interrupt resources. | Required when two independent serial ports are needed on same PCB footprint; not drop-in for single-channel designs. | Select SCC2692AC1A28 only if dual UART functionality is required and board layout accommodates identical PLCC-28 placement. |
| TL16C550CPTR | Industry-standard 16550-compatible UART; 16-byte FIFO (vs. 3-byte), no built-in counter/timer, no address recognition mode. | Better suited for PC-style serial I/O with high interrupt latency tolerance; lacks SCC2691's dual-speed and low-power features. | Choose TL16C550CPTR for cost-sensitive PC peripheral designs where deep FIFO and ISA bus compatibility outweigh custom feature needs. |
Compared with SCC2691AC1A28,512, the SCC2692AC1A28 adds a second UART channel without changing pinout or software interface, while the TL16C550CPTR offers deeper FIFO and broader driver support but omits counter/timer, address recognition, and independent Rx/Tx clocking-making it less suitable for embedded dual-speed or ultra-low-power applications.
Availability
SCC2691AC1A28,512 is available at Aetrix Electronics and suitable for industrial HMI terminals, legacy equipment gateways, multi-processor sensor nodes, and embedded modem control interfaces requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for SCC2691AC1A28,512 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT applications, with roots in Philips' semiconductor division.
The SCC2691 product line was designed for robust, low-power asynchronous serial communication in resource-constrained embedded systems-particularly where dual-speed channels, hardware flow control, and industrial-grade reliability are mandatory.
FAQ
What is the maximum supported baud rate for SCC2691AC1A28,512?
The SCC2691AC1A28,512 supports baud rates up to 115.2 kbaud using its internal baud rate generator or programmable counter/timer. This maximum applies to both receiver and transmitter independently, and is validated across the full industrial temperature range (–40°C to +85°C) with a 3.6864 MHz crystal or equivalent clock source.
Does SCC2691AC1A28,512 support hardware flow control?
Yes, SCC2691AC1A28,512 supports hardware flow control via its MPO and MPI pins. When configured, MPO outputs RTSN (Request to Send), which is automatically negated when the 3-character receiver FIFO is full-and reasserted when space becomes available. MPI can be assigned as CTSN (Clear to Send) input, enabling full RTS/CTS handshake without external logic.
Can SCC2691AC1A28,512 operate with an external clock instead of a crystal?
Yes, SCC2691AC1A28,512 accepts an external clock signal on the X1/CLK pin (0–4 MHz), eliminating the need for a crystal. In this configuration, X2 should be left unconnected or grounded. The device uses this clock directly for baud rate generation, counter/timer, and internal timing-maintaining full functionality including power-down mode and interrupt timing specifications.
What is the purpose of the address recognition mode in SCC2691AC1A28,512?
The address recognition mode in SCC2691AC1A28,512 enables multi-processor wake-up by detecting a dedicated address frame (with A/D bit set) before activating the receiver. This allows slave nodes on a shared bus to remain in low-power state until explicitly addressed-reducing system-wide power consumption and eliminating continuous polling overhead in distributed networks.
How does the power-down mode affect register retention in SCC2691AC1A28,512?
In power-down mode, SCC2691AC1A28,512 freezes its internal oscillator but retains all register contents-including mode, control, status, and counter/timer preset values-without requiring backup power. This allows rapid resumption of serial communication upon exit, with no register reinitialization needed, making it ideal for battery-powered or energy-harvesting applications where wake latency must be minimized.
SCC2691AC1A28,512 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 28-LCC (J-Lead)
- Series:
- -
- Packaging:
- Tube
- Product Status:
- Obsolete
- Features:
- Configurable GPIO, Internal Oscillator, Timer/Counter
- Number of Channels:
- 1, UART
- FIFO's:
- -
- Protocol:
- -
- Data Rate (Max):
- -
- Voltage - Supply:
- 5V
- With Auto Flow Control:
- Yes
- With IrDA Encoder/Decoder:
- -
- With False Start Bit Detection:
- Yes
- With Modem Control:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-PLCC (11.48x11.48)
SCC2691AC1A28,512 FAQ
1.How can I place an order for SCC2691AC1A28,512 through Aetrix?
Please submit a Request for Quotation (RFQ) for SCC2691AC1A28,512 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SCC2691AC1A28,512 reliable?
The price and inventory of SCC2691AC1A28,512 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SCC2691AC1A28,512 is usually 5 days.
3.What payment methods are accepted for SCC2691AC1A28,512?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SCC2691AC1A28,512 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SCC2691AC1A28,512?
SCC2691AC1A28,512 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SCC2691AC1A28,512 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SCC2691AC1A28,512?
For technical support, including SCC2691AC1A28,512 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SCC2691AC1A28,512 requirements.
6.How does Aetrix verify that SCC2691AC1A28,512 is sourced from the original manufacturer or authorized distributors?
All SCC2691AC1A28,512 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SCC2691AC1A28,512 meets industry standards.
7.What is the process for return or replacement of SCC2691AC1A28,512?
All SCC2691AC1A28,512 units undergo pre-shipment inspection (PSI). If there is an issue with SCC2691AC1A28,512, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SCC2691AC1A28,512 part is unused and in its original packaging.
Return procedure for SCC2691AC1A28,512:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SCC2691AC1A28,512 Tags
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SC16IS741AIPWJ
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