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NXP Semiconductors SCC2691AC1N24,602
- Part No.:
- SCC2691AC1N24,602
- Manufacturer:
- NXP Semiconductors
- Package:
- 24-DIP (0.300", 7.62mm)
- Datasheet:
-
SCC2691AC1N24,602.pdf
- Description:
- IC UART SINGLE 24-DIP
- Quantity:
- Payment:
- Shipping:
Inventory:1,645
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Product details
Overview
SCC2691AC1N24 from NXP Semiconductors (formerly Philips Semiconductors) is a CMOS-LSI universal asynchronous receiver/transmitter (UART) providing full-duplex serial communication with quadruple-buffered receiver, independent receiver/transmitter baud rate selection, and integrated 16-bit counter/timer. It operates from a single +5V supply, supports 5–8 data bits, 1/1.5/2 stop bits, and odd/even/no parity, and is used in industrial terminal systems requiring dual-speed channel operation.
For engineers reviewing the SCC2691AC1N24 datasheet, SCC2691AC1N24 pinout, SCC2691AC1N24 application, or SCC2691AC1N24 equivalent, key selection criteria include TTL compatibility, 24-pin DIP package, 0°C to +70°C commercial temperature range, and support for crystal or external clock inputs up to 4 MHz.
Technical Context
The SCC2691AC1N24 implements a fully programmable UART architecture with independent baud rate generators for receiver and transmitter, selectable from 22 fixed rates (50–115.2 kbaud), non-standard user-defined rates via its 16-bit counter/timer, or external 1X/16X clocks. Its timing block integrates an on-chip crystal oscillator (3.6864 MHz nominal) and clock selectors enabling flexible clock source routing.
It features a 3-deep FIFO receiver with RxRDY/FFULL status signaling, automatic RTS flow control tied to FIFO fullness, and multi-function MPO/MPI pins supporting CTS/RTS handshaking, timer outputs, and external clock inputs. The device supports four channel modes: normal full-duplex, automatic echo, local loopback, and remote loopback - all software-configurable via mode registers.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Baud Rate Range | 50 to 115.2 kbaud; includes 22 fixed rates and user-defined non-standard rates via 16-bit counter/timer. |
| Data Format | 5–8 data bits, 1/1.5/2 stop bits (programmable in 1/16-bit increments), odd/even/no/force parity. |
| Receiver Buffering | Quadruple-buffered (3-deep FIFO + shift register); reduces interrupt overhead and prevents overrun in high-throughput systems. |
| Power Supply | +5 V ±10%; draws ≤2.0 mA active current and ≤500 µA in power-down mode. |
| Operating Temperature | 0°C to +70°C (commercial grade); validated across full range per ordering code SCC2691AC1N24. |
| Package | 24-pin plastic dual in-line package (DIP), 300 mil width; pin-compatible with industry-standard UART footprints. |
| Interrupt Architecture | Single open-drain INTRN output with seven maskable sources: TxRDY, TxEMT, RxRDY/FFULL, break change, MPI change, C/T terminal count. |
Pinout & Package
SCC2691AC1N24 is housed in a 24-pin plastic DIP (SOT222–1) with 300 mil body width and 0.3 inch row spacing. Pin 1 is RDN (Read Strobe), pin 24 is VCC, and pin 12 is GND. All pins are TTL-compatible and support 3-state bus interfacing via CEN/WRN/RDN control.
| Pin | Circuit Role | Design Meaning |
|---|---|---|
| 1 | RDN | Active-low read strobe; initiates register read when CEN = low; controls data bus direction with WRN. |
| 2 | RxD | Receiver serial input; samples start bit on falling edge, then at 16X clock center points; supports external 1X/16X clock sync. |
| 3 | TxD | Transmitter serial output; transmits LSB-first with programmable framing; held high (marking) when idle or disabled. |
| 4 | MPO | Multi-purpose output; configurable as RTSN, C/TO, TxC1X/TxC16X, RxC1X/RxC16X, TxRDY, or RxRDY/FFULL (open-drain). |
| 5 | MPI | Multi-purpose input; configurable as CTSN, CTCLK, RTCLK, or GPI; includes internal VCC pull-up (1–4 µA). |
| 6–8 | A0–A2 | Address inputs; select one of eight register sets (MR1/MR2, SR/CSR, RHR/THR, ISR/IMR, CTU/CTUR, CTL/CTLR, ACR, CR). |
| 9 | X1/CLK | Clock input; accepts 3.6864 MHz crystal or external clock up to 4 MHz; drives internal oscillator and baud rate generator. |
| 10 | X2 | Crytal second terminal; left unconnected or grounded if external clock used; no internal drive. |
| 11 | RESET | Master reset; clears SR, IMR, ISR, resets mode pointer to MR1, forces TxD high, disables Tx/Rx. |
| 12 | GND | Ground reference; common return for all signals and power. |
| 13 | INTRN | Active-low interrupt request; open-drain output requiring external pull-up; asserts on any enabled interrupt condition. |
| 14 | CEN | Active-low chip enable; isolates D0–D7 bus when high; enables register access when low with WRN/RDN. |
| 15–22 | D0–D7 | 8-bit bidirectional data bus; LSB = D0, MSB = D7; 3-state controlled by CEN/WRN/RDN; transfers all commands/status/data. |
| 23 | WRN | Active-low write strobe; latches D0–D7 into selected register on rising edge when CEN = low. |
| 24 | VCC | +5 V ±10% power supply; powers all internal logic, oscillator, and I/O buffers. |
Key Features
| Feature | Design Value |
|---|---|
| Independent Rx/Tx Baud Rate Control | Enables dual-speed channel operation (e.g., clustered terminals) using separate clock sources per channel - crystal, counter/timer, or external 1X/16X. |
| Quadruple-Buffered Receiver | 3-character FIFO + shift register minimizes CPU interrupt load and eliminates receiver overrun under burst traffic without hardware flow control. |
| Programmable Channel Modes | Four operational modes - normal full-duplex, automatic echo, local loopback, remote loopback - support diagnostics, protocol testing, and multi-processor wake-up. |
| Integrated 16-Bit Counter/Timer | Configurable as timer (square-wave output) or counter (pulse counting); output routable to MPO; usable for baud rate derivation or system timing. |
| Hardware Flow Control Support | MPO/MPI pins support RTS/CTS handshaking; RTSN automatically deasserts when FIFO fills and reasserts on space availability - prevents data loss. |
| Low-Power Power-Down Mode | Oscillator frozen while register contents retained; current drops to ≤500 µA - suitable for battery-backed or intermittent-communication applications. |
Applications
| Industrial Terminal Systems | Legacy Serial Interface Adapters |
|---|---|
|
Use Scenario: Clustered point-of-sale terminals sharing a central host via RS-232/RS-422 links with asymmetric upstream/downstream data rates. IC Role / Device Role / Timing Role: UART interface IC handling full-duplex serial framing, independent Rx/Tx clocking, and RTS/CTS handshaking between microcontroller and line driver. Use Value: Dual-speed capability allows host to transmit at 115.2 kbaud while terminals reply at 19.2 kbaud - optimizing link utilization without protocol translation. |
Use Scenario: Retrofitting ISA or PCI serial cards in industrial PCs to replace obsolete 16550-compatible UARTs with enhanced buffering and timing flexibility. IC Role / Device Role / Timing Role: Drop-in replacement UART providing TTL-level serial interface with extended register set, FIFO depth, and crystal-oscillator integration. Use Value: Quadruple buffering and programmable stop-bit resolution (1/16-bit) improve reliability in noisy factory-floor RS-232 environments with marginal cable timing margins. |
| Multi-Processor Wake-Up Networks | Embedded Diagnostic Subsystems |
|
Use Scenario: Distributed sensor nodes in building automation systems that remain in low-power sleep until addressed by a master controller over shared UART bus. IC Role / Device Role / Timing Role: Address-frame recognition UART detecting A/D bit patterns to trigger wake-up interrupts without CPU polling. Use Value: Reduces average system power by >90% versus continuous polling; leverages built-in address/data bit tagging and RxRDY assertion on match. |
Use Scenario: In-circuit debug interfaces for legacy 8051 or Z80-based controllers where serial console access must coexist with real-time I/O monitoring. IC Role / Device Role / Timing Role: Dual-role UART supporting simultaneous console logging (via TxD/RxD) and hardware-triggered diagnostic capture (via MPI change interrupt). Use Value: Single-interrupt architecture with seven maskable sources enables precise event correlation - e.g., logging UART traffic while timestamping GPIO transitions. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar UART applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SCC2692AC1N24 | Pin-compatible 24-pin DIP variant with identical register map and timing; adds second UART channel (dual-port) and shared counter/timer. | Required for designs needing two independent serial ports on single chip; not suitable for space-constrained single-UART layouts. | Select SCC2692AC1N24 only when dual-channel operation is mandatory; otherwise SCC2691AC1N24 offers lower cost and footprint. |
| TL16C550CP | Industry-standard 16550A-compatible UART; 16-byte FIFO (vs. 3-byte), no independent Rx/Tx clocking, no counter/timer, no address-frame wake-up. | Preferred for PC-compatible BIOS/OS drivers and legacy OS support; lacks dual-speed and low-power features of SCC2691AC1N24. | Choose TL16C550CP for plug-and-play Windows/Linux compatibility; choose SCC2691AC1N24 for custom embedded control with timing flexibility and power optimization. |
Compared with SCC2692AC1N24, the SCC2691AC1N24 provides single-channel operation with smaller footprint and lower gate count; compared with TL16C550CP, it trades standard FIFO depth for advanced clocking, power management, and multi-processor wake-up - making it optimal for deterministic industrial firmware stacks rather than generic OS drivers.
Availability
SCC2691AC1N24 is available at Aetrix Electronics and suitable for industrial terminal systems, legacy serial interface adapters, multi-processor wake-up networks, and embedded diagnostic subsystems requiring stable component supply, long-lifecycle support, and commercial-grade temperature performance.
Supply support for SCC2691AC1N24 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors (formerly Philips Semiconductors) is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications.
The SCC2691AC1N24 belongs to NXP's legacy communications IC portfolio, designed specifically for robust, low-power, full-duplex serial interface applications in industrial control, point-of-sale, and embedded instrumentation systems.
FAQ
What is the maximum crystal frequency supported by the SCC2691AC1N24?
The SCC2691AC1N24 supports crystal or external clock inputs up to 4.0 MHz, with nominal operation at 3.6864 MHz for standard baud rate generation. The AC Electrical Characteristics table specifies fCLK = 0–4.0 MHz, and timing parameters (e.g., tCLK ≥ 100 ns) are guaranteed across this range. Operation below 2 MHz is design-assured but not production-tested.
Does the SCC2691AC1N24 support automatic hardware flow control?
Yes, the SCC2691AC1N24 supports automatic RTS/CTS flow control via its MPO and MPI pins. When configured, the MPO pin outputs RTSN, which is automatically negated when the 3-character receiver FIFO becomes full and reasserted when space becomes available - preventing receiver overrun without CPU intervention.
Can the SCC2691AC1N24 operate with different baud rates for transmit and receive?
Yes, the SCC2691AC1N24 supports independent baud rate selection for transmitter and receiver. Each channel can be configured to use any of the 22 fixed rates, a non-standard rate derived from the 16-bit counter/timer, or an external 1X/16X clock - enabling dual-speed operation essential for clustered terminal and multi-processor wake-up applications.
What is the function of the A0–A2 address pins on the SCC2691AC1N24?
The A0–A2 pins on the SCC2691AC1N24 select one of eight internal register sets during CPU read/write cycles. Valid combinations include MR1/MR2 (mode registers), SR/CSR (status/clock select), RHR/THR (receive/transmit holding registers), ISR/IMR (interrupt status/mask), CTU/CTUR and CTL/CTLR (counter/timer registers), ACR (auxiliary control), and CR (command register).
Is the SCC2691AC1N24 compatible with 3.3 V logic systems?
No, the SCC2691AC1N24 is strictly a +5 V TTL-compatible device. Its DC Electrical Characteristics specify VIH = 2.0 V minimum (for most pins) and 0.8VCC for X1/CLK, with VOL ≤ 0.4 V and VOH ≥ 2.4 V under load - all referenced to a +5 V ±10% supply. Interfacing with 3.3 V systems requires level-shifting circuitry.
SCC2691AC1N24,602 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 24-DIP (0.300", 7.62mm)
- Series:
- -
- Packaging:
- Tube
- Product Status:
- Obsolete
- Features:
- Configurable GPIO, Internal Oscillator, Timer/Counter
- Number of Channels:
- 1, UART
- FIFO's:
- -
- Protocol:
- -
- Data Rate (Max):
- -
- Voltage - Supply:
- 5V
- With Auto Flow Control:
- Yes
- With IrDA Encoder/Decoder:
- -
- With False Start Bit Detection:
- Yes
- With Modem Control:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 24-DIP
SCC2691AC1N24,602 FAQ
1.How can I place an order for SCC2691AC1N24,602 through Aetrix?
Please submit a Request for Quotation (RFQ) for SCC2691AC1N24,602 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SCC2691AC1N24,602 reliable?
The price and inventory of SCC2691AC1N24,602 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SCC2691AC1N24,602 is usually 5 days.
3.What payment methods are accepted for SCC2691AC1N24,602?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SCC2691AC1N24,602 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SCC2691AC1N24,602?
SCC2691AC1N24,602 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SCC2691AC1N24,602 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SCC2691AC1N24,602?
For technical support, including SCC2691AC1N24,602 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SCC2691AC1N24,602 requirements.
6.How does Aetrix verify that SCC2691AC1N24,602 is sourced from the original manufacturer or authorized distributors?
All SCC2691AC1N24,602 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SCC2691AC1N24,602 meets industry standards.
7.What is the process for return or replacement of SCC2691AC1N24,602?
All SCC2691AC1N24,602 units undergo pre-shipment inspection (PSI). If there is an issue with SCC2691AC1N24,602, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SCC2691AC1N24,602 part is unused and in its original packaging.
Return procedure for SCC2691AC1N24,602:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SCC2691AC1N24,602 Tags
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