NXP Semiconductors SCC2691AE1A28,518
- Part No.:
- SCC2691AE1A28,518
- Manufacturer:
- NXP Semiconductors
- Package:
- 28-LCC (J-Lead)
- Datasheet:
-
SCC2691AE1A28,518.pdf
- Description:
- IC UART CMOS LSI 28PLCC
- Quantity:
- Payment:

- Shipping:

Inventory:3,178
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Product details
Overview
SCC2691AE1A28 from NXP Semiconductors (formerly Philips Semiconductors) is a CMOS-LSI universal asynchronous receiver/transmitter (UART) with full-duplex serial communication, quadruple-buffered receiver FIFO, independent receiver/transmitter baud rate selection, and integrated 16-bit counter/timer. It operates from a single +5V supply and supports industrial temperature range (–40°C to +85°C) in 28-pin PLCC package.
For engineers reviewing the SCC2691AE1A28 datasheet, SCC2691AE1A28 pinout, SCC2691AE1A28 application, or SCC2691AE1A28 equivalent, key selection criteria include dual-speed channel support, programmable data format (5–8 bits, parity options, 1/1.5/2 stop bits), false start bit detection, line break handling, and power-down mode with register retention.
Technical Context
The SCC2691AE1A28 implements a fully programmable UART architecture with independent clock selectors for receiver and transmitter, enabling true dual-speed operation-e.g., 9600 baud receive / 115.2 kbaud transmit. Its 16-bit counter/timer serves both as baud rate source and general-purpose timing resource, configurable via auxiliary control register (ACR) for output on MPO pin.
Receiver logic includes quadruple buffering (3-character FIFO + shift register), automatic RTS flow control based on FIFO full status, and address/data frame recognition for multi-processor wake-up. Transmitter supports break generation, automatic echo, local/remote loopback, and marking-state idle output-all under software control via command and mode registers.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Baud Rates | 18 fixed rates (50–115.2 kbaud); non-standard user-defined via 16-bit counter/timer; external 1X/16X clock support |
| Data Format | 5–8 data bits, odd/even/no/force parity, 1/1.5/2 stop bits programmable in 1/16-bit increments |
| Receiver Buffering | Quadruple buffered: 3-deep FIFO + 1-shift-register stage; reduces overrun risk and interrupt overhead |
| Interrupt System | Single open-drain INTRN output with 7 maskable sources (TxRDY, RxRDY/FFULL, break, MPI change, C/T terminal count) |
| Power Supply | +5 V ±10%; active current ≤2.5 mA (industrial temp), power-down current ≤500 µA |
| Operating Temp | –40°C to +85°C (industrial grade); TTL-compatible I/O; crystal oscillator or external clock input (X1/CLK) |
| Package | 28-pin Plastic Leaded Chip Carrier (PLCC); lead-free per RoHS; pin-compatible with SCC2691AC1A28 (commercial) |
Pinout & Package
SCC2691AE1A28 is housed in a 28-pin PLCC (SOT261-2) package with J-lead configuration, 1.27 mm pitch, and body size 11.5 × 11.5 mm. Pin 1 is located at the index corner adjacent to the notch.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| D0–D7 | Data Bus | 8-bit bidirectional 3-state bus; transfers registers, commands, and status; direction controlled by WRN/RDN under CEN |
| CEN | Chip Enable | Active-low enable for CPU interface; isolates D-bus when high; required for all register access |
| WRN | Write Strobe | Active-low write trigger; latches D0–D7 into register selected by A0–A2 on rising edge |
| RDN | Read Strobe | Active-low read trigger; places selected register contents on D0–D7 on falling edge |
| A0–A2 | Address Inputs | 3-bit register address decoder; selects MR1/MR2, SR/CSR, RHR/THR, ISR/IMR, CTU/CTUR, CTL/CTLR, ACR |
| RESET | Master Reset | Active-high; clears SR, IMR, ISR; resets mode pointer to MR1; forces TxD to marking (high) state |
| INTRN | Interrupt Request | Open-drain active-low output; requires external pull-up; asserts on any unmasked interrupt condition |
| X1/CLK | Clock Input | Crystal or external clock input (0–4 MHz); drives oscillator, BRG, and counter/timer; internal VCC pull-up |
| X2 | Clock Input | Crystal second terminal; floating or grounded if external clock used; no internal pull-up |
| RxD | Receiver Input | Serial data input; sampled on rising edge of RxC (1X) or mid-bit (16X); supports false start detection |
| TxD | Transmitter Output | Serial data output; LSB-first; idle = high (marking); supports break generation and auto-echo modes |
| MPO | Multi-Purpose Output | Programmable function output: RTSN, C/TO, TxC1X/TxC16X, RxC1X/RxC16X, TxRDY, RxRDY/FFULL |
| MPI | Multi-Purpose Input | Configurable input: GPI, CTSN, CTCLK, RTCLK; internal VCC pull-up (1–4 µA); interrupt-capable |
| VCC | Power Supply | +5 V ±10% supply; powers all internal logic and I/O buffers |
| GND | Ground | Reference ground for all signals and power; must be low-impedance connection |
Key Features
| Feature | Design Value |
|---|---|
| Independent Baud Rate Control | Receiver and transmitter each select from 18 fixed rates, counter/timer-derived rates, or external 1X/16X clocks-enabling asymmetric channel designs |
| Quadruple-Buffered Receiver | 3-character FIFO + 1-shift-register stage minimizes overrun in interrupt-driven systems and reduces CPU polling frequency |
| Hardware Flow Control | MPO-configurable RTSN output automatically deasserts when FIFO is full and reasserts on space availability-prevents data loss without software intervention |
| Multi-Processor Address Recognition | Enables wake-up on address frame (A/D bit) detection; reduces slave station power consumption in clustered terminal systems |
| Low-Power Mode | Power-down mode freezes oscillator while preserving register contents; cuts current to ≤500 µA-critical for battery-backed or energy-sensitive applications |
| Comprehensive Error Handling | Detects and flags parity, framing, overrun, false start, and line break conditions-each strobed into status register at character boundary |
Applications
| Industrial Terminal Systems | Multi-Processor Communication Nodes |
|---|---|
|
Use Scenario: Clustered intelligent terminals sharing a common host controller with varying data throughput requirements. IC Role / Device Role / Timing Role: UART channel controller managing asymmetric link speeds-e.g., high-speed host-to-terminal command stream and low-speed terminal-to-host telemetry. Use Value: Independent receiver/transmitter clock selection eliminates need for external clock dividers or dual UARTs, reducing BOM count and PCB area. |
Use Scenario: Distributed sensor network where slave nodes remain in low-power sleep until addressed by master node. IC Role / Device Role / Timing Role: Asynchronous serial interface with address/data frame recognition and automatic wake-up capability. Use Value: Reduces average system current by >90% during idle periods-enabling years of operation on coin-cell batteries. |
| Legacy Equipment Interface Adapters | Embedded Control Panels |
|
Use Scenario: Retrofitting RS-232/RS-422 legacy peripherals into modern microcontroller-based systems with limited GPIO. IC Role / Device Role / Timing Role: Protocol-transparent serial bridge providing hardware handshaking (RTS/CTS), break generation, and flexible framing. Use Value: Eliminates firmware-level UART emulation and enables reliable interoperability with legacy modems, printers, and PLCs. |
Use Scenario: Operator interface panel requiring robust serial communication with host MCU under variable EMI conditions. IC Role / Device Role / Timing Role: Full-duplex UART with false start bit rejection, line break detection, and quadruple buffering for noise immunity. Use Value: Prevents spurious character reception in electrically noisy factory environments-reducing UI lockups and service calls. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar UART applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SCC2692AE1A28 | Pin-compatible upgrade with enhanced FIFO (16-byte depth), additional interrupt sources, and extended baud rate range up to 1 Mbps | Required for high-throughput industrial gateways needing deeper buffering and faster serial links | Select when migrating from SCC2691AE1A28 for higher data volume or future-proofing; same PLCC footprint and register map compatibility |
| TL16C550CPTR | Industry-standard 16550-compatible UART; 16-byte FIFO; no built-in counter/timer; different register layout and interrupt structure | Suitable for PC-compatible BIOS/OS drivers but lacks dual-speed channel and address-frame wake-up features | Choose for cost-sensitive designs leveraging existing 16550 driver stacks; requires PCB redesign due to 48-pin TQFP package and different pinout |
Compared with SCC2691AE1A28, SCC2692AE1A28 offers scalable performance within identical mechanical and electrical constraints, while TL16C550CPTR trades specialized features for broad software ecosystem support-making the former ideal for custom embedded control and the latter for standardized PC-architecture integration.
Availability
SCC2691AE1A28 is available at Aetrix Electronics and suitable for industrial terminal systems, multi-processor communication nodes, and legacy equipment interface adapters requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for SCC2691AE1A28 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT applications, with roots in Philips' pioneering analog and mixed-signal IC development.
The SCC2691 family was designed for robust, low-power asynchronous serial communication in industrial control and clustered terminal systems-emphasizing dual-speed flexibility, hardware flow control, and extended temperature reliability.
FAQ
What is the maximum supported baud rate for SCC2691AE1A28?
The SCC2691AE1A28 supports up to 115.2 kbaud using its internal baud rate generator or counter/timer. When driven by an external 16X clock, it can achieve non-standard rates up to 115.2 kbaud; the device does not support rates beyond this limit per its datasheet specifications. The SCC2691AE1A28's clock selector architecture allows independent configuration for receiver and transmitter, enabling asymmetric operation within this bound.
Does SCC2691AE1A28 support automatic hardware flow control?
Yes, the SCC2691AE1A28 supports automatic RTS flow control via its MPO pin. When configured as RTSN, the output is automatically negated when the 3-character receiver FIFO becomes full and reasserted when space becomes available-enabling real-time overrun prevention without CPU intervention. This behavior is enabled through mode register programming and requires no firmware polling or interrupt servicing.
Can SCC2691AE1A28 operate with an external clock instead of a crystal?
Yes, the SCC2691AE1A28 accepts an external clock signal on the X1/CLK pin, eliminating the need for a crystal. The external clock must be 0–4 MHz, TTL-compatible, and meet specified voltage thresholds (VIL ≤ 0.8 V, VIH ≥ 0.8VCC). When using external clocking, X2 may be left unconnected or grounded. The SCC2691AE1A28 uses this clock directly for its baud rate generator, counter/timer, and internal timing circuits.
What is the receiver FIFO depth of SCC2691AE1A28?
The SCC2691AE1A28 features a quadruple-buffered receiver architecture consisting of a 3-character first-in-first-out (FIFO) queue plus one additional character in the shift register-totaling four stages of buffering. This design significantly reduces the risk of receiver overrun and lowers interrupt overhead in CPU-driven systems. The FFULL status bit asserts when all three FIFO positions are occupied, and RxRDY indicates at least one character is ready for read.
Is SCC2691AE1A28 compatible with the TL16C550 UART register set?
No, the SCC2691AE1A28 uses a proprietary register map distinct from the industry-standard TL16C550. Its address decoding (A0–A2), register layout (MR1/MR2, CSR, ACR, CTUR/CTLR), and interrupt handling differ fundamentally. Firmware written for TL16C550 will not operate correctly on SCC2691AE1A28 without complete register-level reimplementation. The SCC2691AE1A28 is optimized for dual-speed and multi-processor applications-not PC BIOS compatibility.
SCC2691AE1A28,518 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 28-LCC (J-Lead)
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Features:
- Configurable GPIO, Internal Oscillator, Timer/Counter
- Number of Channels:
- 1, UART
- FIFO's:
- -
- Protocol:
- -
- Data Rate (Max):
- -
- Voltage - Supply:
- 5V
- With Auto Flow Control:
- Yes
- With IrDA Encoder/Decoder:
- -
- With False Start Bit Detection:
- Yes
- With Modem Control:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-PLCC (11.48x11.48)
SCC2691AE1A28,518 FAQ
1.How can I place an order for SCC2691AE1A28,518 through Aetrix?
Please submit a Request for Quotation (RFQ) for SCC2691AE1A28,518 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SCC2691AE1A28,518 reliable?
The price and inventory of SCC2691AE1A28,518 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SCC2691AE1A28,518 is usually 5 days.
3.What payment methods are accepted for SCC2691AE1A28,518?
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4.How is shipping managed for SCC2691AE1A28,518?
SCC2691AE1A28,518 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SCC2691AE1A28,518 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SCC2691AE1A28,518?
For technical support, including SCC2691AE1A28,518 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SCC2691AE1A28,518 requirements.
6.How does Aetrix verify that SCC2691AE1A28,518 is sourced from the original manufacturer or authorized distributors?
All SCC2691AE1A28,518 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SCC2691AE1A28,518 meets industry standards.
7.What is the process for return or replacement of SCC2691AE1A28,518?
All SCC2691AE1A28,518 units undergo pre-shipment inspection (PSI). If there is an issue with SCC2691AE1A28,518, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SCC2691AE1A28,518 part is unused and in its original packaging.
Return procedure for SCC2691AE1A28,518:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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