NXP Semiconductors SCC2691AE1A28,602
- Part No.:
- SCC2691AE1A28,602
- Manufacturer:
- NXP Semiconductors
- Package:
- 28-LCC (J-Lead)
- Datasheet:
-
SCC2691AE1A28,602.pdf
- Description:
- IC UART SINGLE 28-PLCC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SCC2691AE1A28 from NXP Semiconductors (formerly Philips Semiconductors) is a CMOS-LSI universal asynchronous receiver/transmitter (UART) providing full-duplex serial communication with quadruple-buffered receiver, independent receiver/transmitter baud rate selection, and 16-bit programmable counter/timer. It operates from a single +5V supply, supports 5–8 data bits, 1/1.5/2 stop bits, and odd/even/no parity, and is used in industrial terminal systems requiring dual-speed channel operation and hardware handshaking.
For engineers reviewing the SCC2691AE1A28 datasheet, SCC2691AE1A28 pinout, SCC2691AE1A28 application, or SCC2691AE1A28 equivalent, key selection criteria include its PLCC-28 package, TTL-compatible I/O, 22 fixed baud rates up to 115.2 kbaud, receiver FIFO full signaling via RxRDY/FFULL, and support for automatic RTS flow control in clustered multi-terminal environments.
Technical Context
The SCC2691AE1A28 implements a fully integrated UART with independent clock selectors for receiver and transmitter paths, enabling simultaneous operation at different baud rates-critical for clustered terminal systems. Its 16-bit counter/timer serves both as a baud rate source and general-purpose timing resource, configurable via auxiliary control register (ACR) bits [6:4] and output-selectable on MPO.
Receiver architecture includes a 3-deep FIFO with status-strobed parity/framing/overrun error detection and false start bit rejection. Transmitter supports break generation, automatic echo, local/remote loopback, and TxRDY signaling. All register access occurs via 8-bit parallel bus (D0–D7) with address decoding (A0–A2), chip enable (CEN), and strobe-controlled read/write (RDN/WRN).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Baud Rates | 22 fixed rates (50–115.2 kbaud); non-standard rates via 16-bit counter/timer or external 1X/16X clock - enables dual-speed channel operation without external logic. |
| Receiver Buffering | Quadruple-buffered (3-deep FIFO + shift register) - reduces interrupt overhead and prevents overrun in interrupt-driven systems. |
| Data Format | 5–8 data bits, odd/even/no/force parity, 1/1.5/2 stop bits in 1/16-bit increments - supports legacy and custom serial protocols including RS-232, RS-422, and proprietary link layers. |
| Power Supply | +5 V ±10% - compatible with standard TTL logic rails and legacy industrial power domains. |
| Operating Temperature | –40°C to +85°C - qualified for industrial embedded applications including factory automation and remote terminal units. |
| Interrupt Output | Single open-drain INTRN with seven maskable sources (TxRDY, RxRDY/FFULL, break, MPI change, counter TC, etc.) - simplifies CPU interrupt handling with centralized status polling via ISR. |
| Crystal Oscillator | On-chip oscillator supporting 3.6864 MHz crystal (X1/CLK–X2) - eliminates need for external clock generator; also accepts external 0–4 MHz clock input. |
Pinout & Package
SCC2691AE1A28 is housed in a 28-pin Plastic Leaded Chip Carrier (PLCC) package with J-lead configuration, lead pitch of 0.05 inch (1.27 mm), and body size 0.472 × 0.472 inch (12.0 × 12.0 mm). The package is RoHS-compliant and rated for industrial temperature operation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| D0–D7 | 8-bit bidirectional data bus | Active-high, 3-state interface to CPU data bus; transfers registers, commands, and status under CEN/RDN/WRN control. |
| A0–A2 | Register address inputs | Selects one of eight internal register sets (MR1/MR2, SR/CSR, RHR/THR, ISR/IMR, CTU/CTUR, CTL/CTLR, ACR, CR) per Table 1. |
| RDN | Active-low read strobe | Initiates register read cycle on falling edge; places selected register contents onto D0–D7 when CEN = low. |
| WRN | Active-low write strobe | Initiates register write cycle on rising edge; latches D0–D7 data into selected register when CEN = low. |
| CEN | Active-low chip enable | Isolates UART from data bus when high; enables all bus operations when low - supports shared-bus multiplexing. |
| INTRN | Active-low interrupt request | Open-drain output asserted on any enabled interrupt condition; requires external pull-up to VCC for proper logic level. |
| RxD | Receiver serial input | Accepts asynchronous serial data; sampled at 16X or 1X clock rate depending on CSR configuration. |
| TxD | Transmitter serial output | Drives serial bit stream with programmable framing; held high (marking) during idle, disable, or loopback modes. |
| MPI | Multi-purpose input | Configurable as CTSN (flow control), RTCLK (external clock), CTCLK (counter clock), or GPI - enables flexible system-level synchronization. |
| MPO | Multi-purpose output | Programmable as RTSN (hardware flow control), TxC1X/TxC16X, RxC1X/RxC16X, C/TO, TxRDY, or RxRDY/FFULL - supports autonomous handshaking and clock distribution. |
| X1/CLK | Clock input | Accepts either 3.6864 MHz crystal or external 0–4 MHz clock; primary timing reference for BRG, counter/timer, and internal logic. |
| X2 | Crystal second terminal | Connected to crystal when using internal oscillator; may be left unconnected or grounded if external clock is used. |
| RESET | Master reset | Asynchronous active-high signal clearing SR, IMR, ISR, and disabling transceiver; sets mode pointer to MR1. |
| VCC / GND | Power supply pins | +5 V ±10% supply and ground reference; decoupling capacitor required near VCC pin for stable operation. |
Key Features
| Feature | Design Value |
|---|---|
| Independent receiver/transmitter clock selection | Enables dual-speed operation (e.g., 9600 bps receive / 19200 bps transmit) without external clock dividers or multiplexers. |
| Hardware RTS/CTS flow control via MPI/MPO | Automatic RTS assertion/negation based on receiver FIFO fill level eliminates software polling and reduces CPU load in high-throughput links. |
| Quadruple-buffered receiver with FFULL flag | 3-character FIFO plus shift register allows up to four characters to be buffered before overrun, supporting bursty traffic in interrupt-driven firmware. |
| 16-bit counter/timer with MPO output routing | Provides precise timing for custom baud rates, pulse-width modulation, or event counting; output selectable on MPO without additional GPIO. |
| Multi-mode operation (normal, echo, loopback) | Supports in-system diagnostics: local loopback verifies transmitter integrity; remote loopback validates end-to-end link; automatic echo aids protocol debugging. |
| Break detection and generation | Hardware detection of continuous low on RxD (break condition) and controlled break transmission via command register - essential for modem control and network reset protocols. |
Applications
| Industrial Terminal Systems | Factory Automation Controllers |
|---|---|
|
Use Scenario: Clustered intelligent terminals sharing a central host controller via multidrop RS-422/485 links. IC Role / Device Role / Timing Role: UART interface managing dual-speed channels: high-speed polling response and low-speed status reporting. Use Value: Independent receiver/transmitter baud rate selection allows host to poll multiple terminals at 38.4 kbaud while receiving status updates at 9.6 kbaud - maximizing bus utilization without protocol translation. |
Use Scenario: PLC backplane or I/O module requiring reliable serial communication with HMI panels and sensor networks. IC Role / Device Role / Timing Role: Full-duplex asynchronous transceiver with hardware flow control interfacing to RS-232/422 peripherals. Use Value: RxRDY/FFULL and RTSN signals enable zero-loss data transfer under variable load; quadruple buffering absorbs burst traffic during motion-control cycles. |
| Legacy Equipment Retrofit | Embedded Diagnostic Interfaces |
|
Use Scenario: Upgrading aging medical or test equipment with modern microcontrollers lacking native UART peripherals. IC Role / Device Role / Timing Role: Standalone UART bridging 8-bit parallel bus (e.g., Z80, 8051) to RS-232 physical layer. Use Value: TTL-compatible D0–D7 interface and +5 V operation match legacy CPU voltage domains; PLCC-28 footprint allows direct replacement of obsolete UARTs like SCN2681. |
Use Scenario: Field-service port on industrial gateways or motor drives for firmware update and real-time debug logging. IC Role / Device Role / Timing Role: Robust serial interface supporting break detection, line break generation, and false start rejection. Use Value: Break detection triggers secure bootloader entry; false start rejection prevents spurious interrupts in electrically noisy cabinet environments. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar UART applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SCN2681C1A28 | Same PLCC-28 package and pinout; lacks 16-bit counter/timer and MPO flexibility; supports only 13 fixed baud rates. | Suitable for basic point-to-point links without dual-speed or timing-critical functions. | Select when cost sensitivity outweighs need for programmable timing or advanced flow control. |
| SCC2692AE1A28 | Pin-compatible upgrade with dual-channel UART (two independent SCC2691 cores), identical register map and timing. | Required for systems needing two isolated serial ports (e.g., Modbus master + debug console) without doubling PCB area. | Choose for higher integration density where dual-port functionality justifies marginal cost increase. |
Compared with SCN2681C1A28, SCC2691AE1A28 delivers greater timing flexibility and hardware flow control; compared with SCC2692AE1A28, it offers lower power and cost for single-channel applications - making it optimal for industrial terminals where one robust UART suffices.
Availability
SCC2691AE1A28 is available at Aetrix Electronics and suitable for industrial terminal systems, factory automation controllers, legacy equipment retrofit, and embedded diagnostic interfaces requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for SCC2691AE1A28 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT applications, with deep heritage in communications ICs dating to Philips Semiconductors.
The SCC2691AE1A28 belongs to NXP's legacy UART product line designed specifically for industrial and embedded systems requiring high reliability, hardware-assisted flow control, and compatibility with aging 8-bit microcontroller buses.
FAQ
What is the maximum baud rate supported by the SCC2691AE1A28?
The SCC2691AE1A28 supports up to 115.2 kbaud using its internal baud rate generator or external clock inputs. This maximum applies to both receiver and transmitter independently, and non-standard rates can be achieved via the 16-bit counter/timer configured to divide the 3.6864 MHz crystal or external clock. The device does not support rates beyond 115.2 kbaud in standard operation per its datasheet specifications.
Does the SCC2691AE1A28 support automatic hardware flow control?
Yes, the SCC2691AE1A28 supports automatic RTS/CTS flow control through its MPI and MPO pins. When configured, the MPO pin outputs RTSN, which is automatically negated when the 3-character receiver FIFO is full and reasserted when space becomes available. The MPI pin can be assigned as CTSN input to gate transmitter activity - enabling hands-off, hardware-managed data flow without CPU intervention.
Can the SCC2691AE1A28 operate with an external clock instead of a crystal?
Yes, the SCC2691AE1A28 can operate with an external clock applied to the X1/CLK pin, ranging from 0 to 4.0 MHz. In this mode, the X2 pin should be left unconnected or grounded. The external clock replaces the crystal oscillator function and serves as the timing reference for the baud rate generator, counter/timer, and internal logic - maintaining full functionality including independent receiver/transmitter clock selection.
What is the purpose of the quadruple buffering in the SCC2691AE1A28 receiver?
The quadruple buffering in the SCC2691AE1A28 receiver consists of a 3-character FIFO plus the receive shift register, minimizing overrun risk during high-speed or bursty serial reception. This architecture reduces interrupt frequency in CPU-driven systems and provides time for firmware to service each character before the next arrives - especially valuable in real-time industrial applications where missed characters compromise system integrity.
Is the SCC2691AE1A28 pin-compatible with other UARTs in the same family?
Yes, the SCC2691AE1A28 is pin-compatible with the SCC2691AC1A28 (commercial version) and shares identical pinout and register mapping with the SCN2681C1A28 in PLCC-28 package. However, it is not pin-compatible with DIP-24 or SOL-24 variants due to differing package footprints and pin counts - mechanical and electrical compatibility must be verified per package type.
SCC2691AE1A28,602 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 28-LCC (J-Lead)
- Series:
- -
- Packaging:
- Tube
- Product Status:
- Discontinued at Digi-Key
- Features:
- Configurable GPIO, Internal Oscillator, Timer/Counter
- Number of Channels:
- 1, UART
- FIFO's:
- -
- Protocol:
- -
- Data Rate (Max):
- -
- Voltage - Supply:
- 5V
- With Auto Flow Control:
- Yes
- With IrDA Encoder/Decoder:
- -
- With False Start Bit Detection:
- Yes
- With Modem Control:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-PLCC (11.48x11.48)
SCC2691AE1A28,602 FAQ
1.How can I place an order for SCC2691AE1A28,602 through Aetrix?
Please submit a Request for Quotation (RFQ) for SCC2691AE1A28,602 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SCC2691AE1A28,602 reliable?
The price and inventory of SCC2691AE1A28,602 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SCC2691AE1A28,602 is usually 5 days.
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4.How is shipping managed for SCC2691AE1A28,602?
SCC2691AE1A28,602 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SCC2691AE1A28,602 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SCC2691AE1A28,602?
For technical support, including SCC2691AE1A28,602 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SCC2691AE1A28,602 requirements.
6.How does Aetrix verify that SCC2691AE1A28,602 is sourced from the original manufacturer or authorized distributors?
All SCC2691AE1A28,602 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SCC2691AE1A28,602 meets industry standards.
7.What is the process for return or replacement of SCC2691AE1A28,602?
All SCC2691AE1A28,602 units undergo pre-shipment inspection (PSI). If there is an issue with SCC2691AE1A28,602, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SCC2691AE1A28,602 part is unused and in its original packaging.
Return procedure for SCC2691AE1A28,602:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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