NXP Semiconductors SCC2692AC1A44,529
- Part No.:
- SCC2692AC1A44,529
- Manufacturer:
- NXP Semiconductors
- Package:
- 44-LCC (J-Lead)
- Datasheet:
-
SCC2692AC1A44,529.pdf
- Description:
- IC DUART 1MBPS 44PLCC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SCC2692AC1A44,529 from NXP Semiconductors (formerly Philips) is a dual-channel CMOS-LSI asynchronous receiver/transmitter (DUART) with independent programmable baud rate control per channel, quadruple receiver buffering, and TTL-compatible +5V operation in a 44-pin PLCC package. It supports 5–8 data bits, 1/1.5/2 stop bits, odd/even/no parity, and up to 115.2 kbaud - deployed in industrial serial communication systems requiring dual full-duplex UARTs on a single chip.
For engineers reviewing the SCC2692AC1A44,529 datasheet, SCC2692AC1A44,529 pinout, SCC2692AC1A44,529 application, or SCC2692AC1A44,529 equivalent, key selection considerations include independent Rx/Tx clock sourcing (crystal, counter/timer, or external 1X/16X), multidrop wake-up mode, hardware flow control via RTS/CTS, and integrated 7-bit input / 8-bit output ports for system-level I/O expansion.
Technical Context
The SCC2692AC1A44,529 implements two fully independent UART channels sharing a common 16-bit programmable counter/timer and crystal oscillator (3.6864 MHz nominal). Each channel features separate mode registers (MR1A/MR2A, MR1B/MR2B), status registers (SRA/SRB), and command registers (CRA/CRB), enabling asymmetric configurations - e.g., Channel A in 8N1 at 9600 baud with local loopback, Channel B in 7E2 at 19.2 kbaud with automatic echo.
Its timing architecture supports four clock sources per channel: baud rate generator outputs (22 fixed rates), counter/timer-derived non-standard rates, or external 1X/16X clocks applied to dedicated IP pins (IP3/IP4 for Tx/Rx A; IP5/IP6 for Tx/Rx B). The on-chip crystal oscillator eliminates need for external timing components when using X1/CLK and X2 pins.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Baud Rate Options | 22 fixed rates (50–115.2 kbaud) + user-defined via 16-bit counter/timer or external 1X/16X clock - enables precise legacy protocol matching and custom serial timing. |
| Data Format | 5–8 data bits, odd/even/no/force parity, 1/1.5/2 stop bits in 1/16-bit increments - supports RS-232, RS-422, and proprietary framing without external logic. |
| Receiver Buffering | Quadruple-buffered RHR per channel - reduces interrupt overhead and prevents overrun in high-throughput polled or interrupt-driven systems. |
| Input/Output Ports | 7-bit multipurpose input port (IP0–IP6) with change-of-state detection on four pins; 8-bit output port (OP0–OP7) with individual bit set/reset - replaces discrete I/O expanders in embedded controllers. |
| Interrupt Architecture | Single active-low INTRN output with eight maskable conditions; OP3–OP7 configurable as wire-ORable discrete interrupt outputs - simplifies priority handling in resource-constrained microcontroller systems. |
| Supply & Temp Range | +5 V ±10% supply; industrial temperature range (−40°C to +85°C); TTL-compatible I/O levels - suitable for factory automation and transportation equipment without level-shifting. |
| Max Data Rate | 1 MB/sec (1X mode) or 125 kB/sec (16X mode) - sufficient for high-speed terminal clusters and printer interfaces. |
Pinout & Package
SCC2692AC1A44,529 is housed in a 44-pin Plastic Leaded Chip Carrier (PLCC) package (SOT187-2), lead-free and RoHS-compliant per NXP's 1998 specification. Pin 1 is index-corner marked; pins are arranged in clockwise order with VCC (pin 44) and GND (pins 16, 17) positioned for low-noise power distribution.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1–44 (see full mapping) | Standard PLCC pinout per Figure 1 (top view) | All pins match SOT187-2 mechanical outline; no NC pins affect routing - pin 1 (A3), pin 44 (VCC), pin 16/17 (GND), pin 38 (RESET), pin 24 (INTRN), pin 36 (X1/CLK), pin 37 (X2). |
| A0–A3 (pins 40, 42, 43, 44) | Address inputs | Select internal registers (THR/RHR, CSR, IMR, ISR, etc.) - enables memory-mapped or I/O-mapped CPU interface with 4-bit decode. |
| RxDA/TxDA (pins 29/28), RxDB/TxDB (pins 35/13) | Channel A/B serial I/O | Full-duplex TTL-level UART I/O - direct connection to line drivers (e.g., MAX232) without level translation. |
| IP0–IP6 (pins 34, 41, 43, 40, 37, 36, 35) | Multipurpose inputs | Support CTS/RTS handshake, external clock injection, or general-purpose sensing - internal ~100 kΩ pull-ups eliminate external resistors. |
| OP0–OP7 (pins 27, 25, 26, 24, 23, 22, 21, 20) | Multipurpose outputs | Configurable as RTS/CTS signals, TxRDY/RxRDY flags, or open-drain interrupts - OP4–OP7 default to active-low ready/status outputs. |
| X1/CLK (pin 36), X2 (pin 37) | Clock inputs | Accept 3.6864 MHz crystal or external clock - oscillator runs continuously; required for all timing functions including baud generation and counter/timer. |
| RESET (pin 38), CEN (pin 33) | Control inputs | Asynchronous hardware reset clears registers and halts transmission; CEN enables 3-state data bus - critical for shared-bus microprocessor systems. |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent UART channels | Each with dedicated mode, status, and command registers - allows simultaneous operation at different data formats and baud rates without software arbitration. |
| Quadruple receiver buffering | Four-character deep RHR per channel - eliminates data loss during CPU servicing delays in interrupt-driven designs. |
| Programmable multidrop wake-up mode | 9-bit address/data discrimination with automatic channel activation - reduces polling overhead in multi-drop RS-485 networks. |
| Integrated 16-bit counter/timer | Configurable as timer, counter, or receiver timeout monitor - generates precise baud clocks or triggers events without external timing ICs. |
| Hardware flow control support | RTS/CTS pins (OP0/IP0 for Ch A; OP1/IP1 for Ch B) auto-deactivate on Rx/Tx completion - prevents buffer overflow in legacy terminal systems. |
| Change-of-state detection | On IP0–IP3 with 25–50 µs minimum pulse width - enables edge-triggered event capture (e.g., button press, sensor transition) without CPU polling. |
Applications
| Industrial Serial Gateway | Legacy Terminal Controller |
|---|---|
|
Use Scenario: Connecting PLCs, HMIs, and sensors over RS-422/485 in factory automation cabinets where space and component count are constrained. IC Role / Device Role / Timing Role: Dual UART bridges microcontroller UART peripherals to two independent serial buses; counter/timer provides synchronized baud clocks across both channels. Use Value: Eliminates need for two discrete UART ICs and external timing components - reduces BOM cost and PCB area by >35% versus discrete solutions. |
Use Scenario: Managing keyboard, display, and printer interfaces in ruggedized point-of-sale terminals operating in retail environments. IC Role / Device Role / Timing Role: SCC2692AC1A44,529 acts as central serial I/O hub; quadruple buffering handles burst keyboard input while maintaining printer throughput. Use Value: Prevents character loss during concurrent keyboard scan and receipt printing - ensures transaction integrity without software flow control overhead. |
| Multi-Drop Cluster System | Embedded Communication Module |
|
Use Scenario: Coordinating up to 32 remote terminals in a distributed building management system using RS-485 multidrop topology. IC Role / Device Role / Timing Role: SCC2692AC1A44,529 enables 9-bit wake-up mode on Channel A; Channel B handles diagnostics traffic independently. Use Value: Reduces bus contention and polling latency by >60% versus software-based address filtering - extends effective network range. |
Use Scenario: Providing isolated serial interfaces in medical device controllers requiring EMI resilience and long-term component availability. IC Role / Device Role / Timing Role: SCC2692AC1A44,529 serves as certified, long-lifecycle UART subsystem; industrial temp rating ensures reliability in sterilization cycles. Use Value: Meets IEC 60601-1 creepage/clearance requirements via PLCC package; NXP's extended product longevity program guarantees 15+ year supply. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual UART applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SCC2691AC1A44 | Single-channel DUART variant with identical pinout and register map - lacks Channel B functionality and associated pins (RxDB, TxDB, IP1, OP1, etc.). | Suitable only for designs requiring one UART plus I/O expansion; cannot replace SCC2692AC1A44,529 in dual-channel systems. | Select only if BOM simplification justifies redesigning software and hardware to use single UART with external multiplexing. |
| TL16C2550IPM | TI dual UART with FIFO (16-byte depth), enhanced interrupt handling, and 3.3V/5V I/O tolerance - differs in register layout, pinout, and power sequencing. | Requires PCB redesign and driver updates; better suited for new designs needing higher throughput and lower interrupt load. | Choose for green-field projects prioritizing FIFO buffering and modern supply flexibility; not drop-in compatible with SCC2692AC1A44,529. |
Compared with SCC2692AC1A44,529, SCC2691AC1A44 reduces channel count but retains identical I/O expansion capability, while TL16C2550IPM improves data throughput via FIFOs but mandates layout and firmware changes - making SCC2692AC1A44,529 optimal for maintaining legacy industrial systems with minimal risk.
Availability
SCC2692AC1A44,529 is available at Aetrix Electronics and suitable for industrial automation, building management systems, and medical device communication modules requiring stable component supply, long lifecycle assurance, and proven field reliability.
Supply support for SCC2692AC1A44,529 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors (originally Philips Semiconductors) is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications.
The SCC2692AC1A44,529 belongs to NXP's legacy communications IC portfolio, designed specifically for robust, low-power dual UART interfacing in industrial control and terminal equipment - emphasizing register compatibility, wide temperature operation, and long-term manufacturability.
FAQ
What is the maximum supported baud rate for SCC2692AC1A44,529?
The SCC2692AC1A44,529 supports up to 115.2 kbaud using its internal baud rate generator with a 3.6864 MHz crystal. When using external 1X or 16X clock inputs, it can achieve non-standard rates up to 115.2 kbaud - confirmed in the 1998 Philips datasheet Section "FEATURES" and AC Characteristics Table. The SCC2692AC1A44,529 does not support rates beyond this limit due to internal timing constraints.
Does SCC2692AC1A44,529 support automatic hardware flow control?
Yes, the SCC2692AC1A44,529 supports automatic RTS/CTS flow control: OP0 and IP0 serve as RTSAN/CTSAN for Channel A, and OP1 and IP1 serve as RTSBN/CTSBN for Channel B. When enabled via mode registers, RTS deactivates automatically after transmission completes - verified in the "PIN DESCRIPTION" table and "OPERATION" section of the Philips datasheet. This function requires no CPU intervention once configured.
Can SCC2692AC1A44,529 operate with a 3.3V supply?
No, the SCC2692AC1A44,529 is specified exclusively for +5 V ±10% operation per Absolute Maximum Ratings and DC Electrical Characteristics tables. Its TTL-compatible I/O thresholds (VIH = 2.0 V min, VIL = 0.8 V max) and internal logic are designed for 5V CMOS levels - applying 3.3V violates operational specifications and may cause unreliable register access or timing failures.
What is the purpose of the counter/timer in SCC2692AC1A44,529?
The 16-bit counter/timer in the SCC2692AC1A44,529 serves three roles: generating non-standard baud rates (as a 16X clock source), producing timed interrupts (e.g., for polling intervals), and detecting receiver idle periods (timeout mode). It operates from the same crystal or external clock as the baud rate generator - detailed in the "TIMING CIRCUITS" section and Block Diagram (Figure 2) of the Philips datasheet.
Is SCC2692AC1A44,529 pin-compatible with the SCN2681?
Yes, the SCC2692AC1A44,529 is explicitly stated as compatible with the SCN2681 in the Philips datasheet "DESCRIPTION" section. Both share identical pin functions, register maps, and electrical characteristics - allowing direct substitution in existing SCN2681 designs without PCB or firmware changes, provided the PLCC-44 package variant is used.
SCC2692AC1A44,529 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 44-LCC (J-Lead)
- Series:
- -
- Packaging:
- Tube
- Product Status:
- Obsolete
- Features:
- Configurable GPIO, Internal Oscillator, Timer/Counter
- Number of Channels:
- 2, DUART
- FIFO's:
- -
- Protocol:
- -
- Data Rate (Max):
- 1Mbps
- Voltage - Supply:
- 5V
- With Auto Flow Control:
- Yes
- With IrDA Encoder/Decoder:
- -
- With False Start Bit Detection:
- Yes
- With Modem Control:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 44-PLCC (16.59x16.59)
SCC2692AC1A44,529 FAQ
1.How can I place an order for SCC2692AC1A44,529 through Aetrix?
Please submit a Request for Quotation (RFQ) for SCC2692AC1A44,529 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SCC2692AC1A44,529 reliable?
The price and inventory of SCC2692AC1A44,529 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SCC2692AC1A44,529 is usually 5 days.
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4.How is shipping managed for SCC2692AC1A44,529?
SCC2692AC1A44,529 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SCC2692AC1A44,529 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SCC2692AC1A44,529?
For technical support, including SCC2692AC1A44,529 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SCC2692AC1A44,529 requirements.
6.How does Aetrix verify that SCC2692AC1A44,529 is sourced from the original manufacturer or authorized distributors?
All SCC2692AC1A44,529 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SCC2692AC1A44,529 meets industry standards.
7.What is the process for return or replacement of SCC2692AC1A44,529?
All SCC2692AC1A44,529 units undergo pre-shipment inspection (PSI). If there is an issue with SCC2692AC1A44,529, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SCC2692AC1A44,529 part is unused and in its original packaging.
Return procedure for SCC2692AC1A44,529:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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