NXP Semiconductors SCC2692AC1B44,557
- Part No.:
- SCC2692AC1B44,557
- Manufacturer:
- NXP Semiconductors
- Package:
- 44-QFP
- Datasheet:
-
SCC2692AC1B44,557.pdf
- Description:
- IC UART DUAL W/FIFO 44QFP
- Quantity:
- Payment:

- Shipping:

Inventory:1,680
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SCC2692AC1B44,557 from NXP Semiconductors (formerly Philips) is a dual-channel CMOS universal asynchronous receiver/transmitter (DUART) in 44-pin PQFP package, supporting independent programmable baud rates up to 115.2 kbaud per channel, quadruple-buffered receivers, and TTL-compatible +5 V operation. It interfaces directly with microprocessors via an 8-bit bidirectional data bus and supports polled or interrupt-driven communication in industrial serial systems.
For engineers reviewing the SCC2692AC1B44,557 datasheet, SCC2692AC1B44,557 pinout, SCC2692AC1B44,557 application, or SCC2692AC1B44,557 equivalent, key selection considerations include independent Rx/Tx clock sourcing (crystal, counter/timer, or external 1X/16X), multidrop wake-up mode, receiver timeout, and dual 7-/8-bit multipurpose I/O ports for status/interrupt signaling.
Technical Context
The SCC2692AC1B44,557 integrates two fully independent UART channels sharing a single 16-bit programmable counter/timer and crystal oscillator (3.6864 MHz nominal). Each channel supports separate configuration of data format (5–8 bits, odd/even/no parity, 1/1.5/2 stop bits), operating mode (normal, loopback, multidrop), and baud rate source - including 22 fixed rates, non-standard rates derived from the counter/timer, or external clocks.
Its interrupt architecture features one active-low open-drain INTRN output with eight maskable sources plus six wire-ORable discrete interrupt outputs assignable to OP3–OP7. The 7-bit input port includes change-of-state detection on IP0–IP3, while the 8-bit output port supports individual bit set/reset and configurable function assignment (e.g., TxRDYAN, RxRDYBN, CTSN).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Baud Rate Range | 50 to 115.2 kbaud per channel; selectable from 22 fixed rates, counter/timer-derived non-standard rates, or external 1X/16X clock inputs. |
| Data Format | Programmable per channel: 5–8 data bits, odd/even/no/force parity, 1/1.5/2 stop bits in 1/16-bit increments. |
| Receiver Buffering | Quadruple-buffered RHR per channel minimizes overrun risk and reduces interrupt overhead in high-throughput serial links. |
| Supply Voltage | +5 V ±10%; operates across commercial (0 to +70°C) and industrial (−40 to +85°C) temperature ranges. |
| Crystal Oscillator | On-chip oscillator supports 2–4 MHz crystals (nominal 3.6864 MHz); X1/CLK accepts external clock input if crystal not used. |
| Interrupt Outputs | Single active-low INTRN plus up to six discrete open-drain interrupt outputs (OP3–OP7) for TxRDY/RxRDY/CT/counter events. |
| I/O Ports | 7-bit input port (IP0–IP6) with internal ~100 kΩ pull-ups and change-of-state detection; 8-bit output port (OP0–OP7) with individual bit set/reset control. |
Pinout & Package
SCC2692AC1B44,557 uses a 44-pin plastic quad flat pack (PQFP) package (SOT307-2), lead-free and RoHS-compliant per original Philips specification. Pin functions are validated per Figure 1 (PQFP top view) and Pin Description table in the 1998 product specification.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1–4, 40–44 | A3–A0, VCC, IP4–IP2, CEN, RESET | Address inputs (A0–A3), +5 V supply (VCC), general-purpose inputs (IP2–IP4), chip enable (CEN), hardware reset (RESET). |
| 5–8, 36–39 | RxDB, TxDB, RxDA, TxDA, X1/CLK, X2, CEN, RESET | Serial data I/O for Channel B (RxDB/TxDB) and Channel A (RxDA/TxDA); crystal/clock inputs (X1/CLK, X2); shared control signals. |
| 9–12, 28–35 | WRN, RDN, D0–D7, OP0–OP7 | Write/read strobes (WRN/RDN), 8-bit bidirectional data bus (D0–D7), and 8-bit programmable output port (OP0–OP7). |
| 13–27, 41–43 | INTRN, IP0–IP6, OP1–OP7 | Active-low interrupt request (INTRN), 7-bit input port (IP0–IP6), and functional outputs (e.g., OP4 = RxRDYAN, OP6 = TxRDYAN). |
| 22, 38 | GND | Dual ground pins ensure stable reference for analog timing circuits and digital I/O. |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent UART channels | Each supports full-duplex asynchronous communication with separate data format, mode, and baud rate configuration. |
| Quadruple receiver buffering | Reduces CPU interrupt frequency and prevents character loss during burst reception without flow control. |
| Multidrop wake-up mode | Enables selective activation of remote terminals in clustered systems using 9-bit address framing. |
| Receiver timeout detection | Automatically flags pauses in incoming data stream, enabling protocol-level idle detection and error recovery. |
| Programmable counter/timer | 16-bit down-counter usable as baud rate source, timer, or receiver timeout monitor with interrupt capability. |
| Flexible I/O port mapping | IP0–IP6 and OP0–OP7 support dynamic reassignment as clock/control inputs or status/interrupt outputs under software control. |
Applications
| Industrial Serial Gateway | Legacy Terminal Interface |
|---|---|
|
Use Scenario: Connecting PLCs, HMIs, and sensors over RS-232/422 to a central controller in factory automation. IC Role / Device Role / Timing Role: DUART provides dual isolated serial channels with independent baud rate control and hardware flow control (RTS/CTS) for deterministic polling. Use Value: Quadruple receiver buffering ensures no data loss during high-speed polling cycles; receiver timeout enables robust detection of disconnected devices. |
Use Scenario: Retrofitting aging CRT terminals and printers with modern microcontroller-based host systems. IC Role / Device Role / Timing Role: Acts as a drop-in serial interface bridge, translating parallel CPU bus transactions into asynchronous serial streams with legacy timing compliance. Use Value: TTL-compatible I/O and +5 V operation eliminate level-shifting components; multidrop mode supports daisy-chained terminal clusters. |
| Embedded Modem Control | Test Equipment Data Link |
|
Use Scenario: Managing AT command exchange and data path switching between microcontroller and modem IC in portable comms devices. IC Role / Device Role / Timing Role: One channel handles command/response traffic (AT commands), the other manages high-throughput data transfer with independent clocking. Use Value: Independent Rx/Tx clock sources allow simultaneous use of standard (e.g., 9600 bps) and non-standard (e.g., 115200 bps) rates without timing conflict. |
Use Scenario: Synchronizing data capture and stimulus generation in automated test fixtures using UART-triggered sequences. IC Role / Device Role / Timing Role: DUART generates precise timing signals (via OP2/OP3 clock outputs) and captures timestamped serial responses using change-of-state detection on IP inputs. Use Value: On-chip counter/timer and input port change detection provide hardware-assisted event timing without CPU intervention. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual UART applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SCC2691AC1B44 | Single-channel version; identical pinout and register map but only one UART channel and reduced I/O port size. | Suitable where only one serial interface is required; lacks Channel B functionality and associated OP/IP pins. | Select SCC2691AC1B44 only when system design requires exactly one UART and board space is constrained. |
| TL16C2550IPM | Enhanced FIFO (16-byte per channel), higher max baud rate (1.5 Mbps), 3.3 V tolerant I/O, but requires external clock and lacks on-chip oscillator. | Supports higher-speed protocols (e.g., IrDA, GPS modules); incompatible with crystal-only designs requiring no external clock source. | Choose TL16C2550IPM for new designs needing deeper buffering and 3.3 V compatibility; avoid if crystal-based timing is mandatory. |
Compared with SCC2692AC1B44,557, SCC2691AC1B44 reduces channel count and I/O flexibility but maintains footprint compatibility, while TL16C2550IPM trades integrated crystal support and legacy voltage compatibility for higher throughput and FIFO depth - making it unsuitable as a drop-in replacement but viable for performance-upgraded redesigns.
Availability
SCC2692AC1B44,557 is available at Aetrix Electronics and suitable for industrial serial gateways, legacy terminal interfaces, embedded modem control, test equipment data links, and multidrop cluster systems requiring stable component supply and long-term obsolescence management.
Supply support for SCC2692AC1B44,557 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors (originally Philips Semiconductors) is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications.
The SCC2692AC1B44,557 belongs to NXP's legacy communications IC portfolio, designed specifically for reliable, low-power dual-channel serial interfacing in industrial control, point-of-sale, and telecom infrastructure equipment.
FAQ
What is the maximum supported baud rate for SCC2692AC1B44,557?
The SCC2692AC1B44,557 supports a maximum baud rate of 115.2 kbaud per channel when using the internal baud rate generator with a 3.6864 MHz crystal. Higher rates up to 130.4 kbaud are documented in the datasheet for specific configurations, but 115.2 kbaud is the highest standard rate guaranteed across commercial and industrial temperature ranges for SCC2692AC1B44,557.
Does SCC2692AC1B44,557 include an on-chip crystal oscillator?
Yes, SCC2692AC1B44,557 integrates an on-chip crystal oscillator. It operates with a 2–4 MHz crystal (nominal 3.6864 MHz) connected between X1/CLK and X2 pins. If an external clock is preferred, it can be applied to X1/CLK while leaving X2 unconnected or grounded - the oscillator circuitry remains functional in either configuration.
How many interrupt sources does SCC2692AC1B44,557 support?
SCC2692AC1B44,557 supports eight maskable interrupt sources routed to the single active-low INTRN output: receiver ready, transmitter ready, receiver break, receiver framing/parity/overrun errors, counter/timer expiration, and input port change. Additionally, OP3–OP7 can be configured as six discrete open-drain interrupt outputs for dedicated signaling.
Can SCC2692AC1B44,557 operate with different baud rates on each channel?
Yes, SCC2692AC1B44,557 allows fully independent baud rate selection for Channel A and Channel B. Each channel can use any of 22 fixed rates, a non-standard rate derived from the shared 16-bit counter/timer, or an external 1X or 16X clock applied to dedicated IP pins - enabling dual-speed operation essential for clustered terminal systems.
What is the function of the IP0–IP6 and OP0–OP7 pins on SCC2692AC1B44,557?
IP0–IP6 form a 7-bit input port with internal pull-ups (~100 kΩ) and change-of-state detection on IP0–IP3; they can serve as general-purpose inputs or dedicated signals like CTSN or external clock sources. OP0–OP7 constitute an 8-bit output port supporting individual bit set/reset and configurable functions such as TxRDYAN, RxRDYBN, or counter/timer outputs - all programmable via OPR, OPCR, and mode registers.
SCC2692AC1B44,557 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 44-QFP
- Series:
- -
- Packaging:
- Tray
- Product Status:
- Obsolete
- Features:
- Configurable GPIO, Internal Oscillator, Timer/Counter
- Number of Channels:
- 2, DUART
- FIFO's:
- -
- Protocol:
- -
- Data Rate (Max):
- 1Mbps
- Voltage - Supply:
- 5V
- With Auto Flow Control:
- Yes
- With IrDA Encoder/Decoder:
- -
- With False Start Bit Detection:
- Yes
- With Modem Control:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 44-PQFP (10x10)
SCC2692AC1B44,557 FAQ
1.How can I place an order for SCC2692AC1B44,557 through Aetrix?
Please submit a Request for Quotation (RFQ) for SCC2692AC1B44,557 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SCC2692AC1B44,557 reliable?
The price and inventory of SCC2692AC1B44,557 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SCC2692AC1B44,557 is usually 5 days.
3.What payment methods are accepted for SCC2692AC1B44,557?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SCC2692AC1B44,557 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SCC2692AC1B44,557?
SCC2692AC1B44,557 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SCC2692AC1B44,557 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SCC2692AC1B44,557?
For technical support, including SCC2692AC1B44,557 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SCC2692AC1B44,557 requirements.
6.How does Aetrix verify that SCC2692AC1B44,557 is sourced from the original manufacturer or authorized distributors?
All SCC2692AC1B44,557 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SCC2692AC1B44,557 meets industry standards.
7.What is the process for return or replacement of SCC2692AC1B44,557?
All SCC2692AC1B44,557 units undergo pre-shipment inspection (PSI). If there is an issue with SCC2692AC1B44,557, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SCC2692AC1B44,557 part is unused and in its original packaging.
Return procedure for SCC2692AC1B44,557:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SCC2692AC1B44,557 Tags

-
SC16IS741AIPWJ
NXP Semiconductors

-
TL16C550CPTR
Texas Instruments

-
TL16C550CIPTR
Texas Instruments

-
SC16C752BIB48,128
NXP Semiconductors

-
ST16C2550CQ48-F
MaxLinear, Inc.

-
ST16C2550CJ44-F
MaxLinear, Inc.

-
ST16C2552CJ44-F
MaxLinear, Inc.

-
ST16C1550IQ48-F
MaxLinear, Inc.

-
ST16C2550IQ48-F
MaxLinear, Inc.

-
ST16C554DIQ64-F
MaxLinear, Inc.

-
ST16C554DCQ64-F
MaxLinear, Inc.
-
XR17V352IB113-F
MaxLinear, Inc.
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

