NXP Semiconductors SCC2692AE1A44,512
- Part No.:
- SCC2692AE1A44,512
- Manufacturer:
- NXP Semiconductors
- Package:
- 44-LCC (J-Lead)
- Datasheet:
-
SCC2692AE1A44,512.pdf
- Description:
- IC DUART DUAL W/FIFO 44-PLCC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SCC2692AE1A44,512 from NXP Semiconductors (formerly Philips) is a dual-channel CMOS universal asynchronous receiver/transmitter (DUART) in 44-pin PLCC package, operating at +5V, supporting independent programmable baud rates up to 115.2 kbaud per channel, quadruple receiver buffering, and TTL-compatible bus interface for microprocessor systems.
For engineers reviewing the SCC2692AE1A44,512 datasheet, SCC2692AE1A44,512 pinout, SCC2692AE1A44,512 application, or SCC2692AE1A44,512 equivalent, key selection considerations include dual full-duplex UART channel independence, 16-bit programmable counter/timer, multidrop wake-up mode, on-chip crystal oscillator, and industrial temperature range (–40°C to +85°C) operation.
Technical Context
The SCC2692AE1A44,512 implements two independent UART channels (A and B), each with fully programmable data format (5–8 data bits, odd/even/no/force parity, 1/1.5/2 stop bits), separate receiver/transmitter clock sources (22 fixed baud rates, counter/timer-derived, or external 1X/16X), and false start bit detection. Its timing block integrates a crystal oscillator (X1/CLK, X2), baud rate generator, and 16-bit counter/timer supporting timer, counter, and receiver timeout modes.
It features a single 8-bit bidirectional data bus (D0–D7) with address decoding (A0–A3), active-low chip enable (CEN), read/write strobes (RDN/WRN), and interrupt architecture with one shared open-drain INTRN output plus six wire-ORable interrupt-capable output port pins (OP0–OP7). The 7-bit input port (IP0–IP6) includes change-of-state detection on four inputs and internal ~100 kΩ pull-ups.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Function | Dual full-duplex asynchronous receiver/transmitter (DUART) with independent channel control |
| Supply Voltage | +5 V ±10% - compatible with standard TTL logic rails and legacy microprocessor buses |
| Operating Temperature | –40°C to +85°C - qualified for industrial embedded applications without derating |
| Baud Rate Range | 50 to 115.2 kbaud per channel - supports RS-232, RS-422, and proprietary serial protocols |
| Receiver Buffering | Quadruple depth per channel - reduces interrupt overhead and prevents overrun in high-throughput polled systems |
| Counter/Timer | 16-bit programmable - enables custom baud rate generation, time-delay functions, or receiver timeout monitoring |
| Crystal Oscillator | On-chip - eliminates external oscillator components when using 3.6864 MHz crystal across X1/CLK–X2 |
| Interrupt Architecture | Single INTRN output with eight maskable sources + six configurable OP pins - supports flexible system-level interrupt routing |
Pinout & Package
SCC2692AE1A44,512 is housed in a 44-pin plastic leaded chip carrier (PLCC) package (SOT187-2), surface-mount compatible with gull-wing leads, 1.27 mm pitch, and index corner marking. Pin 1 is located at the index corner (top-left when notch faces up).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (A3) | Address Input | Selects internal register address bit 3 during CPU read/write cycles |
| 2 (IP0) | Input Port Bit 0 | General-purpose input or Channel A CTS#; internal ~100 kΩ pull-up to VCC |
| 3 (WRN) | Write Strobe | Active-low signal initiating register write on rising edge when CEN is low |
| 4 (RDN) | Read Strobe | Active-low signal initiating register read on falling edge when CEN is low |
| 5 (RxDB) | Channel B Receiver Input | Serial data input for UART Channel B; sampled on rising edge of 1X clock or 16X center sampling |
| 6 (TxDB) | Channel B Transmitter Output | Serial data output for UART Channel B; least-significant bit first, mark = high |
| 24 (OP6) | Output Port Bit 6 | Configurable as TxRDYAN (active-low) or general-purpose output; open-drain when used as interrupt |
| 25 (OP4) | Output Port Bit 4 | Configurable as RxRDYAN/FFULLAN (active-low) or general-purpose output |
| 38 (RESET) | Hardware Reset | Active-high signal clearing all registers, halting counter/timer, and forcing Tx outputs to mark state |
| 44 (VCC) | Power Supply | +5 V supply input; decoupling required near pin for noise immunity |
Key Features
| Feature | Design Value |
|---|---|
| Independent channel baud rate selection | Each UART channel (A/B) selects from 22 fixed rates, counter/timer-derived non-standard rates, or external 1X/16X clocks - enables dual-speed terminal clustering |
| Multidrop wake-up mode | Supports 9-bit addressing with automatic "break" detection and interrupt generation - eliminates polling in multi-drop bus topologies |
| Receiver timeout detection | Monitors idle RxD line after character reception; asserts interrupt if no new start bit detected within programmable window - prevents hang in half-duplex systems |
| Programmable flow control | Remote transmitter disable via FFULL status and OP4/OP5 assertion - prevents buffer overflow without software handshake |
| Change-of-state detection | Hardware detection on IP0–IP3 with interrupt capability - offloads CPU from polling mechanical switch or sensor edges |
| Power-down mode | Reduces ICC to ≤10 µA - extends battery life in portable serial interfaces while retaining register state |
Applications
| Industrial Serial Gateway | Legacy Terminal Controller |
|---|---|
Use Scenario: Connecting Modbus RTU field devices to a central PLC via isolated RS-485 links. IC Role / Device Role / Timing Role: DUART provides two independent full-duplex serial ports: one for upstream master communication, one for downstream slave polling. Use Value: Quadruple receiver buffering prevents data loss during burst polling; independent baud rate control allows simultaneous 9600 bps (PLC link) and 19200 bps (sensor network) operation. | Use Scenario: Emulating VT100 terminal behavior in a ruggedized point-of-sale terminal with keyboard and printer interfaces. IC Role / Device Role / Timing Role: SCC2692AE1A44,512 acts as the primary serial I/O controller, handling keyboard scan codes and printer command streams concurrently. Use Value: Automatic echo and local loopback modes simplify firmware development; multidrop wake-up supports daisy-chained peripherals without dedicated address lines. |
| Medical Device Data Logger | Avionics Maintenance Interface |
Use Scenario: Capturing diagnostic telemetry from ECG and SpO₂ modules over RS-232 into flash memory on a low-power embedded controller. IC Role / Device Role / Timing Role: Dual UART channels manage real-time sensor streaming (Channel A) and buffered log upload via maintenance port (Channel B). Use Value: Receiver timeout mode detects cable disconnect or module failure; power-down mode cuts idle current to <10 µA between acquisition intervals. | Use Scenario: Interfacing ground support equipment with aircraft ARINC 429 or MIL-STD-1553 test adapters via RS-232 debug ports. IC Role / Device Role / Timing Role: SCC2692AE1A44,512 serves as the host-side serial bridge, translating command packets and parsing response frames under strict timing constraints. Use Value: False start bit rejection and line break detection ensure robust frame synchronization in electrically noisy hangar environments; industrial temp rating guarantees operation at –40°C ambient. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual UART applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SCC2691AE1A44 | Single-channel version; identical pinout and register map but only Channel A implemented | Lower pin count not required; lacks Channel B functionality entirely | Select only if system requires exactly one UART and board space is constrained |
| TL16C550CPN | Enhanced FIFO (16-byte), auto RTS/CTS, enhanced interrupt handling; 48-pin TQFP vs. 44-pin PLCC | Requires PCB redesign; supports higher throughput but lacks multidrop wake-up and counter/timer | Prefer for new designs needing FIFO buffering and hardware flow control; not drop-in compatible |
Compared with SCC2692AE1A44,512, the SCC2691AE1A44 sacrifices channel count for footprint reduction, while the TL16C550CPN trades legacy feature support (multidrop, counter/timer, power-down) for modern FIFO efficiency and flow-control automation - neither is pin-compatible, requiring layout revision.
Availability
SCC2692AE1A44,512 is available at Aetrix Electronics and suitable for industrial serial gateways, legacy terminal controllers, medical data loggers, avionics maintenance interfaces, and embedded communication subsystems requiring stable component supply across extended product lifecycles.
Supply support for SCC2692AE1A44,512 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company formed from the spin-off of Philips' semiconductor division, specializing in secure connectivity, automotive, industrial, and IoT solutions.
The SCC2692AE1A44,512 belongs to NXP's legacy communications IC portfolio, designed specifically for robust, long-lifecycle embedded serial interfacing in industrial and aerospace applications where reliability, temperature resilience, and backward compatibility are critical.
FAQ
What is the maximum supported baud rate for each channel of the SCC2692AE1A44,512?
The SCC2692AE1A44,512 supports a maximum baud rate of 115.2 kbaud per channel. This is achieved using the on-chip baud rate generator with a 3.6864 MHz crystal or external clock. Non-standard rates up to 115.2 kbaud are also possible via the 16-bit programmable counter/timer, enabling precise matching to proprietary protocol requirements in the SCC2692AE1A44,512.
Does the SCC2692AE1A44,512 include an integrated crystal oscillator?
Yes, the SCC2692AE1A44,512 includes an on-chip crystal oscillator circuit. It operates with a 3.6864 MHz crystal connected between pins X1/CLK and X2. Alternatively, an external clock signal in the 0–4 MHz range may be applied to X1/CLK, bypassing the crystal. This oscillator serves as the timing reference for the baud rate generator, counter/timer, and internal logic in the SCC2692AE1A44,512.
How does the quadruple receiver buffering in the SCC2692AE1A44,512 improve system performance?
The quadruple receiver buffering in the SCC2692AE1A44,512 allows up to four characters to be stored in each channel's receive path before overrun occurs. This significantly reduces interrupt frequency in interrupt-driven systems and minimizes data loss during CPU servicing delays. In polled systems, it lowers the required polling rate, freeing CPU bandwidth - a key advantage in resource-constrained microcontroller applications using the SCC2692AE1A44,512.
Can the SCC2692AE1A44,512 operate in multidrop (9-bit) mode, and how is it enabled?
Yes, the SCC2692AE1A44,512 supports multidrop (also called 'wake-up' or '9-bit') mode. It is enabled by programming the Mode Register (MR1) for each channel to select multidrop mode and configuring the receiver to detect break conditions. Upon detecting a break, the SCC2692AE1A44,512 asserts an interrupt and loads the subsequent address byte - allowing selective activation of slaves on a shared bus without continuous polling.
What are the power supply requirements and current consumption specifications for the SCC2692AE1A44,512?
The SCC2692AE1A44,512 requires a single +5 V ±10% supply (VCC) and draws 10 mA typical in active operation. In power-down mode, supply current drops to ≤10 µA. These values are specified across the full industrial temperature range (–40°C to +85°C), making the SCC2692AE1A44,512 suitable for battery-backed or thermally demanding applications without additional regulation or derating.
SCC2692AE1A44,512 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 44-LCC (J-Lead)
- Series:
- -
- Packaging:
- Tube
- Product Status:
- Obsolete
- Features:
- Configurable GPIO, Internal Oscillator, Timer/Counter
- Number of Channels:
- 2, DUART
- FIFO's:
- -
- Protocol:
- -
- Data Rate (Max):
- 1Mbps
- Voltage - Supply:
- 5V
- With Auto Flow Control:
- Yes
- With IrDA Encoder/Decoder:
- -
- With False Start Bit Detection:
- Yes
- With Modem Control:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 44-PLCC (16.59x16.59)
SCC2692AE1A44,512 FAQ
1.How can I place an order for SCC2692AE1A44,512 through Aetrix?
Please submit a Request for Quotation (RFQ) for SCC2692AE1A44,512 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SCC2692AE1A44,512 reliable?
The price and inventory of SCC2692AE1A44,512 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SCC2692AE1A44,512 is usually 5 days.
3.What payment methods are accepted for SCC2692AE1A44,512?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SCC2692AE1A44,512 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SCC2692AE1A44,512?
SCC2692AE1A44,512 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SCC2692AE1A44,512 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SCC2692AE1A44,512?
For technical support, including SCC2692AE1A44,512 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SCC2692AE1A44,512 requirements.
6.How does Aetrix verify that SCC2692AE1A44,512 is sourced from the original manufacturer or authorized distributors?
All SCC2692AE1A44,512 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SCC2692AE1A44,512 meets industry standards.
7.What is the process for return or replacement of SCC2692AE1A44,512?
All SCC2692AE1A44,512 units undergo pre-shipment inspection (PSI). If there is an issue with SCC2692AE1A44,512, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SCC2692AE1A44,512 part is unused and in its original packaging.
Return procedure for SCC2692AE1A44,512:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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