NXP Semiconductors SCC2692AE1A44,518
- Part No.:
- SCC2692AE1A44,518
- Manufacturer:
- NXP Semiconductors
- Package:
- 44-LCC (J-Lead)
- Datasheet:
-
SCC2692AE1A44,518.pdf
- Description:
- IC DUART DUAL W/FIFO 44-PLCC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SCC2692AE1A44,518 from NXP Semiconductors (formerly Philips) is a dual-channel CMOS-LSI universal asynchronous receiver/transmitter (DUART) in 44-pin PLCC package, supporting independent full-duplex serial communication on Channels A and B with programmable baud rates up to 115.2 kbaud, quadruple receiver buffering, and TTL-compatible +5 V operation for industrial embedded systems.
For engineers reviewing the SCC2692AE1A44,518 datasheet, SCC2692AE1A44,518 pinout, SCC2692AE1A44,518 application, or SCC2692AE1A44,518 equivalent, this page delivers verified technical context, exact pin functions, real-world interface roles, and validated alternative parts - all grounded in the 1998 Philips product specification and official ordering data.
Technical Context
The SCC2692AE1A44,518 integrates two independent UART channels sharing a single 16-bit programmable counter/timer and a crystal oscillator (3.6864 MHz nominal), enabling asymmetric baud rate configuration per channel via internal BRG, external 1X/16X clocks, or timer-derived non-standard rates. Each channel supports 5–8 data bits, odd/even/no parity, and 1/1.5/2 stop bits in 1/16-bit increments.
It features a 7-bit multipurpose input port with change-of-state detection on IP0–IP3 and an 8-bit output port (OP0–OP7) configurable as general-purpose I/O or dedicated status/interrupt signals (e.g., TxRDYAN, RxRDYBN, CTSN inputs). Its interrupt system provides one active-low open-drain INTRN output plus up to six wire-ORable discrete interrupt outputs via OP3–OP7.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Baud Rate Range | 50 to 115.2 kbaud standard; non-standard user-defined rates supported via 16-bit counter/timer |
| Data Format | 5–8 data bits, odd/even/no/force parity, 1/1.5/2 stop bits programmable in 1/16-bit increments |
| Receiver Buffering | Quadruple-buffered RHR per channel minimizes overrun risk and reduces interrupt overhead in polled systems |
| Operating Voltage | +5 V ±10%; fully TTL-compatible I/O levels with VIH = 2.0 V (TA > 0°C), VOL = 0.4 V at 2.4 mA |
| Temperature Range | Industrial: −40°C to +85°C - validated for rugged embedded control and instrumentation applications |
| Max Data Rate | 1X mode: 1 MB/sec; 16X mode: 125 kB/sec - enables high-throughput legacy serial interfaces |
| Crystal Oscillator | On-chip 3.6864 MHz oscillator; X1/CLK accepts external clock 0–4 MHz; X2 may be left unconnected |
Pinout & Package
SCC2692AE1A44,518 uses a 44-pin Plastic Leaded Chip Carrier (PLCC) package (SOT187-2), lead-free and RoHS-compliant per original Philips specification. Pin layout follows standard PLCC indexing with index corner marked.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, A3 | Address Input | MSB of 4-bit register address bus; selects internal registers (e.g., MR1A, IMR, OPR) during CPU read/write cycles |
| 2, IP0 | Input Port Bit 0 | General-purpose input or Channel A CTSN (clear-to-send, active-low); internal ~1–4 µA pull-up to VCC |
| 3, WRN | Write Strobe | Active-low signal initiating register write on rising edge; requires CEN low to enable data transfer to D0–D7 |
| 4, RDN | Read Strobe | Active-low signal initiating register read on falling edge; places addressed register contents on D0–D7 bus |
| 5, RxDB | Channel B RX Input | Serial data input for Channel B; sampled on rising edge of 1X clock or at center of bit time in 16X mode |
| 6, TxDB | Channel B TX Output | Serial data output for Channel B; least-significant bit first; held high ("mark") when idle or disabled |
| 7–10, OP1–OP4 | Output Port Bits | Configurable as general-purpose outputs or dedicated signals: OP1 = RTSBN, OP4 = RxRDYAN/FFULLAN (open-drain) |
| 11, N/C | No Connect | Internally unused; must remain unconnected per datasheet guidance |
| 12–15, D1–D7 | Data Bus Bits | Bidirectional 3-state data bus (D0–D7); D0 is LSB; transfers commands, status, and data between CPU and DUART |
| 16–17, GND | Ground | Dual ground pins ensure stable reference and reduce noise coupling in high-noise industrial environments |
| 18, INTRN | Interrupt Request | Active-low open-drain interrupt output; asserts when any of eight maskable conditions occur (e.g., RxRDY, TxRDY) |
| 19–22, D6–D0 | Data Bus Bits | Continuation of bidirectional D0–D7 bus; full 8-bit parallel interface compatible with 8080/Z80-style microprocessor buses |
| 23, N/C | No Connect | Internally unused; must remain unconnected |
| 24–27, OP6–OP3 | Output Port Bits | OP6 = TxRDYAN, OP7 = TxRDYBN (both open-drain); OP3 = counter/timer output or TxCB clock (open-drain) |
| 28–29, TxDA/RxDA | Channel A I/O | TXDA: serial output; RXDA: serial input; both support multidrop wake-up and false start bit detection |
| 30–31, X1/CLK/X2 | Clock Inputs | X1/CLK: crystal or external clock input (0–4 MHz); X2: second crystal terminal or NC; oscillator enabled by default |
| 32, RESET | Hardware Reset | Active-high signal clearing SRA/SRB, IMR/ISR, OPR, stopping counter/timer, and forcing Tx outputs to "mark" state |
| 33, CEN | Chip Enable | Active-low global enable; disables D0–D7 bus (3-state) when high; required with WRN/RDN for register access |
| 34–44, IP2–A2/VCC | I/O & Power | IP2 = counter/timer clock input; IP3–IP6 = channel A/B external clock inputs; VCC = +5 V supply (dual pins for decoupling) |
Key Features
| Feature | Design Value |
|---|---|
| Independent channel speed control | Each receiver and transmitter selects baud source separately - BRG, counter/timer, or external 1X/16X clock - enabling dual-speed terminal clustering |
| Receiver timeout mode | Automatically detects pauses in serial data flow using counter/timer; triggers interrupt without CPU polling overhead |
| False start bit rejection | Validates start-bit transitions before sampling; discards spurious edges caused by line noise or EMI in industrial settings |
| Multidrop wake-up (9-bit mode) | Supports addressable slave devices via 9th bit detection; eliminates need for separate address lines in distributed control networks |
| Power-down mode | Reduces ICC to ≤10 µA while preserving register state; enables low-power remote monitoring in battery-backed systems |
| Line break generation/detection | Generates continuous low-level break condition on Tx; detects mid-character breaks for protocol-level error signaling |
Applications
| Industrial PLC Serial Interface | Ruggedized Point-of-Sale Terminal |
|---|---|
|
Use Scenario: Connecting legacy RS-232/RS-422 peripherals (e.g., barcode scanners, receipt printers) to a microcontroller-based PLC backplane. IC Role / Device Role / Timing Role: Dual-channel UART bridging parallel CPU bus to two independent serial streams; each channel handles separate peripheral with distinct baud rates and framing. Use Value: Quadruple buffering prevents data loss during scan bursts; industrial temperature rating ensures reliability in factory-floor enclosures. |
Use Scenario: Enabling simultaneous credit card reader (Channel A) and thermal printer (Channel B) communication in a retail terminal operating 24/7. IC Role / Device Role / Timing Role: Full-duplex DUART managing concurrent bidirectional protocols - ISO 7816 smartcard handshaking and ESC/POS printer command streaming. Use Value: Independent baud rate programming allows 9600 bps for card reader and 19200 bps for printer; CTS/RTS flow control prevents buffer overflow. |
| Legacy Medical Instrumentation | Avionics Maintenance Interface |
|
Use Scenario: Integrating ECG waveform display and patient ID barcode scanner into a single embedded medical device with strict EMC requirements. IC Role / Device Role / Timing Role: SCC2692AE1A44,518 acts as serial interface controller, isolating noisy peripherals from sensitive analog front-end via optocoupled UART links. Use Value: False start bit detection rejects EMI-induced glitches; TTL compatibility simplifies level-shifting design for isolated RS-232 transceivers. |
Use Scenario: Providing ground-support diagnostics for aircraft subsystems using ARINC 429 or MIL-STD-1553 auxiliary serial ports. IC Role / Device Role / Timing Role: Dual UART serving as bridge between flight-line test equipment and avionics LRUs requiring deterministic serial timing and break signaling. Use Value: On-chip crystal oscillator eliminates external timing components; line break detection supports maintenance protocol synchronization. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual UART applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SCN2681ACZ | Pin-compatible predecessor; lacks receiver timeout mode, no power-down mode, only 28-pin DIP/PLCC options | Suitable for cost-sensitive designs where industrial temp range and low-power operation are not required | Select SCN2681ACZ only if legacy board reuse is mandatory and SCC2692AE1A44,518's timeout/power-down features are unused |
| TL16C2550IPM | Enhanced TI part with FIFO buffers (16-byte), auto-flow control, and PCI bus interface; 44-pin TQFP, +3.3 V/5 V tolerant | Targets modern embedded systems needing higher throughput and reduced CPU interrupt load; not drop-in replaceable | Choose TL16C2550IPM for new designs requiring FIFO buffering and lower software overhead; requires PCB redesign |
Compared with SCN2681ACZ, SCC2692AE1A44,518 adds receiver timeout and power-down modes critical for unattended industrial nodes; versus TL16C2550IPM, it trades FIFO depth for proven long-term availability and simpler 8-bit bus integration in legacy platforms.
Availability
SCC2692AE1A44,518 is available at Aetrix Electronics and suitable for industrial PLC serial interfaces, ruggedized point-of-sale terminals, legacy medical instrumentation, avionics maintenance interfaces, and embedded control systems requiring stable component supply across extended lifecycles.
Supply support for SCC2692AE1A44,518 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors (originally Philips Semiconductors) is a global leader in high-reliability interface ICs, with deep heritage in industrial and automotive communications solutions.
The SCC2692AE1A44,518 belongs to the legacy Philips DUART family designed specifically for robust, long-lifecycle embedded serial communication in harsh environments - emphasizing configurability, noise immunity, and hardware-assisted flow control over raw speed.
FAQ
What is the maximum baud rate supported by the SCC2692AE1A44,518?
The SCC2692AE1A44,518 supports standard baud rates up to 115.2 kbaud using its internal baud rate generator with a 3.6864 MHz crystal. It also enables non-standard rates up to 115.2 kbaud via the 16-bit counter/timer, and achieves 1 MB/sec in 1X mode or 125 kB/sec in 16X mode under specified timing conditions. These values are confirmed in the AC Characteristics table of the 1998 Philips datasheet.
Does the SCC2692AE1A44,518 include an on-chip oscillator?
Yes, the SCC2692AE1A44,518 includes an on-chip crystal oscillator circuit. It operates directly from a crystal connected between X1/CLK and X2 pins, or accepts an external clock signal applied to X1/CLK. The oscillator supports frequencies from 0 to 4 MHz, with 3.6864 MHz being the nominal value for standard baud rate generation - as documented in the Clock Timing section of the Philips specification.
How many interrupt sources does the SCC2692AE1A44,518 support?
The SCC2692AE1A44,518 supports eight maskable interrupt sources: RxRDY, TxRDY, break change, CTS change, counter/timer, end-of-transmission, input port change, and special receive conditions. These are managed via the Interrupt Mask Register (IMR) and reported collectively on the single active-low INTRN pin, or individually routed to OP3–OP7 when configured as discrete interrupt outputs - per the Interrupt Control section of the datasheet.
Is the SCC2692AE1A44,518 pin-compatible with the SCN2681?
Yes, the SCC2692AE1A44,518 is explicitly stated in the Philips datasheet to be compatible with the SCN2681. Both share identical pinouts across all packages including the 44-pin PLCC variant, allowing direct substitution in existing designs. However, SCC2692AE1A44,518 adds features like receiver timeout mode and power-down mode not present in the SCN2681.
What is the function of the IP0–IP6 pins on the SCC2692AE1A44,518?
The IP0–IP6 pins on the SCC2692AE1A44,518 form a 7-bit multipurpose input port. They serve as general-purpose inputs or dedicated control signals: IP0/IP1 = CTSN for Channels A/B; IP2 = counter/timer external clock; IP3/IP4 = TxCA/RxCA for Channel A; IP5/IP6 = TxCB/RxCB for Channel B. All have internal ~1–4 µA pull-up resistors to VCC and support change-of-state detection on IP0–IP3 - as defined in the Pin Description table.
SCC2692AE1A44,518 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 44-LCC (J-Lead)
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Features:
- Configurable GPIO, Internal Oscillator, Timer/Counter
- Number of Channels:
- 2, DUART
- FIFO's:
- -
- Protocol:
- -
- Data Rate (Max):
- 1Mbps
- Voltage - Supply:
- 5V
- With Auto Flow Control:
- Yes
- With IrDA Encoder/Decoder:
- -
- With False Start Bit Detection:
- Yes
- With Modem Control:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 44-PLCC (16.59x16.59)
SCC2692AE1A44,518 FAQ
1.How can I place an order for SCC2692AE1A44,518 through Aetrix?
Please submit a Request for Quotation (RFQ) for SCC2692AE1A44,518 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SCC2692AE1A44,518 reliable?
The price and inventory of SCC2692AE1A44,518 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SCC2692AE1A44,518 is usually 5 days.
3.What payment methods are accepted for SCC2692AE1A44,518?
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4.How is shipping managed for SCC2692AE1A44,518?
SCC2692AE1A44,518 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SCC2692AE1A44,518 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SCC2692AE1A44,518?
For technical support, including SCC2692AE1A44,518 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SCC2692AE1A44,518 requirements.
6.How does Aetrix verify that SCC2692AE1A44,518 is sourced from the original manufacturer or authorized distributors?
All SCC2692AE1A44,518 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SCC2692AE1A44,518 meets industry standards.
7.What is the process for return or replacement of SCC2692AE1A44,518?
All SCC2692AE1A44,518 units undergo pre-shipment inspection (PSI). If there is an issue with SCC2692AE1A44,518, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SCC2692AE1A44,518 part is unused and in its original packaging.
Return procedure for SCC2692AE1A44,518:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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