NXP Semiconductors SCC2692AE1B44,551
- Part No.:
- SCC2692AE1B44,551
- Manufacturer:
- NXP Semiconductors
- Package:
- 44-QFP
- Datasheet:
-
SCC2692AE1B44,551.pdf
- Description:
- IC UART DUAL W/FIFO 44QFP
- Quantity:
- Payment:

- Shipping:

Inventory:1,624
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SCC2692AE1B44,551 from NXP Semiconductors (formerly Philips) is a dual-channel CMOS-LSI asynchronous receiver/transmitter (DUART) operating at +5V with industrial temperature range (−40°C to +85°C), 44-pin PQFP package (SOT307–2), and independent programmable baud rates up to 115.2 kbaud per channel - used in legacy industrial serial communication systems requiring two full-duplex UARTs on a single chip.
For engineers reviewing the SCC2692AE1B44,551 datasheet, SCC2692AE1B44,551 pinout, SCC2692AE1B44,551 application, or SCC2692AE1B44,551 equivalent, key selection considerations include its quadruple-buffered receivers, 16-bit programmable counter/timer, multidrop wake-up mode, TTL-compatible bus interface, and support for external 1X/16X clock inputs - critical for deterministic serial I/O in embedded control and terminal systems.
Technical Context
The SCC2692AE1B44,551 implements two independent UART channels (A and B), each with fully programmable data format (5–8 data bits, odd/even/no parity, 1/1.5/2 stop bits), separate receiver/transmitter baud rate selection from 22 fixed rates or user-defined via counter/timer, and false start bit detection. Its timing subsystem integrates an on-chip crystal oscillator (3.6864 MHz nominal), 16-bit counter/timer with timer/counter/time-out modes, and four clock selectors enabling independent clock routing per channel.
It features a single 8-bit bidirectional data bus (D0–D7), 4-bit address bus (A0–A3), active-low chip enable (CEN), read/write strobes (RDN/WRN), and a shared open-drain interrupt output (INTRN) with eight maskable conditions. The device supports local/remote loopback, automatic echo, and multidrop (9-bit) mode - all configurable via internal registers accessible through memory-mapped I/O.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Function | Dual full-duplex asynchronous receiver/transmitter (DUART) with independent channel configuration |
| Supply Voltage | +5 V ±10% - compatible with standard TTL logic rails and legacy 5V microprocessor buses |
| Operating Temperature | −40°C to +85°C - qualified for industrial environments without derating |
| Baud Rate Range | 50 to 115.2 kbaud per channel, selectable from 22 fixed rates or non-standard via 16-bit counter/timer |
| Receiver Buffer Depth | Quadruple-buffered - reduces interrupt overhead and prevents overrun in high-throughput polled/interrupt-driven systems |
| Package | 44-pin plastic quad flat pack (PQFP), SOT307–2 - surface-mount compatible with automated assembly |
| Crystal Oscillator | On-chip, supports 3.6864 MHz crystal across X1/CLK and X2 - eliminates need for external oscillator circuitry |
| Interrupt Architecture | Single active-low open-drain INTRN output with eight maskable sources; OP3–OP7 configurable as discrete wire-ORable interrupts |
Pinout & Package
SCC2692AE1B44,551 uses a 44-pin PQFP package (SOT307–2) with 0.8 mm lead pitch and exposed thermal pad (not electrically connected). Pin functions are defined per Philips Semiconductors Product Specification Rev. 1998 Sep 04.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1–4, 40–44 | A3, IP0, WRN, RDN, A0–A3, VCC | Address/data control interface: A0–A3 select internal registers; WRN/RDN control register access timing; VCC powers core logic |
| 5–12, 19–22 | RxDB, TxDB, OP1–OP7, D0–D7, GND | Serial I/O and parallel interface: RxDB/TxDB handle Channel B serial data; D0–D7 form bidirectional 8-bit CPU bus; GND is signal reference |
| 13–18, 23–39 | OP0, IP2–IP6, CEN, RESET, X1/CLK, X2, INTRN, TxDA, RxDA | System integration signals: CEN enables bus transactions; RESET initializes registers; X1/CLK+X2 host crystal; INTRN signals interrupt events |
Key Features
| Feature | Design Value |
|---|---|
| Independent baud rate programming | Each channel selects from 22 fixed rates or custom rate via 16-bit counter/timer - enables dual-speed operation (e.g., host ↔ terminal) |
| Quadruple receiver buffering | Four-level FIFO per channel minimizes CPU polling frequency and prevents data loss during interrupt latency |
| Multidrop (9-bit/wake-up) mode | Enables selective addressing in multi-drop RS-485 networks by detecting address-break sequences - no external protocol logic required |
| Programmable input port change detection | Hardware detects transitions on IP0–IP3 with >25 µs pulse width; sets status bits and optionally triggers interrupts - offloads GPIO monitoring from CPU |
| Open-drain interrupt outputs | OP4–OP7 can be configured as active-low RxRDY/TxRDY/FFULL signals - allows direct connection to microcontroller interrupt pins without level-shifting |
| Power-down mode | Reduces ICC to ≤10 µA - preserves system power during idle periods while retaining register state |
Applications
| Industrial Serial Terminal Interface | Legacy PLC Communication Module |
|---|---|
Use Scenario: Connecting ASCII terminals or operator panels to a central controller over RS-232/RS-422 links in factory automation cabinets. IC Role / Device Role / Timing Role: DUART provides two independent full-duplex serial ports; one handles HMI command/response, the other manages diagnostics logging. Use Value: Quadruple buffering ensures no character loss at 9600 baud under heavy interrupt load; multidrop mode supports daisy-chained displays without external address decoders. | Use Scenario: Adding dual serial interfaces to a programmable logic controller for Modbus RTU master/slave operation and firmware update channel. IC Role / Device Role / Timing Role: SCC2692AE1B44,551 acts as the physical layer UART; its 16-bit counter/timer generates precise 9600/19200 baud clocks synchronized to internal system timing. Use Value: Independent receiver/transmitter clocking allows simultaneous Modbus master polling (Channel A) and slave response handling (Channel B) without timing conflict. |
| Embedded Point-of-Sale System | Ruggedized Data Acquisition Gateway |
Use Scenario: Integrating receipt printer (RS-232) and magnetic stripe reader (TTL-level serial) into a compact retail terminal with limited PCB space. IC Role / Device Role / Timing Role: Dual UART bridges disparate peripherals to a single microcontroller bus; OP0/OP1 serve as RTS handshake lines. Use Value: TTL-compatible I/O eliminates level translators; programmable stop bits (1/1.5/2) match legacy peripheral timing requirements without firmware adaptation. | Use Scenario: Aggregating sensor data from multiple RS-485 field devices in oil/gas telemetry enclosures operating at −40°C ambient. IC Role / Device Role / Timing Role: SCC2692AE1B44,551 serves as the serial front-end for a Cortex-M4-based gateway; its industrial temp grade ensures reliability without forced air cooling. Use Value: On-chip crystal oscillator simplifies BOM; receiver timeout mode detects cable disconnects; power-down mode extends battery life during sleep cycles. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual UART applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SCC2691AE1B44 | Single-channel version of same family; identical pinout except Channel B signals repurposed as I/O or unused | Suitable only when one UART suffices; lacks Channel B serial I/O and associated registers | Select SCC2691AE1B44 if system requires only one serial port and board layout rework must be avoided |
| MAX3100EAP+ | SPITM interface instead of parallel bus; integrated transceivers; operates from 2.7–5.5 V; no on-chip oscillator | Requires SPI host controller; supports hot-swap; lacks multidrop mode and counter/timer | Choose MAX3100EAP+ for new designs needing low-voltage operation, smaller footprint, and SPI-native microcontrollers |
Compared with SCC2691AE1B44, the SCC2692AE1B44,551 delivers true dual-channel independence and multidrop capability, while MAX3100EAP+ trades parallel bus compatibility and legacy feature depth for modern interface simplicity and wider supply range - making SCC2692AE1B44,551 irreplaceable in maintained industrial hardware where register-level software compatibility is mandatory.
Availability
SCC2692AE1B44,551 is available at Aetrix Electronics and suitable for industrial serial terminal interfaces, legacy PLC communication modules, and ruggedized data acquisition gateways requiring stable component supply across extended product lifecycles.
Supply support for SCC2692AE1B44,551 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company formed from the spin-off of Philips' semiconductor division, specializing in secure connectivity solutions for automotive, industrial, and IoT applications.
The SCC2692 product line was designed for embedded industrial systems requiring robust, register-compatible dual UART functionality with minimal external components - targeting long-lifecycle applications in manufacturing, energy, and transportation infrastructure.
FAQ
What is the maximum supported baud rate for SCC2692AE1B44,551?
The SCC2692AE1B44,551 supports a maximum baud rate of 115.2 kbaud per channel, achievable using either the internal baud rate generator with a 3.6864 MHz crystal or via external 1X/16X clock inputs. Non-standard rates up to this limit are also supported through the 16-bit programmable counter/timer. The device does not support rates beyond 115.2 kbaud due to internal timing constraints documented in the 1998 specification.
Does SCC2692AE1B44,551 include an on-chip crystal oscillator?
Yes, the SCC2692AE1B44,551 integrates an on-chip crystal oscillator that operates directly from a 3.6864 MHz crystal connected between X1/CLK and X2 pins. This eliminates the need for an external oscillator circuit. The oscillator is functional across the full industrial temperature range (−40°C to +85°C) and is referenced in the Absolute Maximum Ratings and Clock Timing sections of the official Philips specification.
Can SCC2692AE1B44,551 operate with a 3.3 V supply?
No, the SCC2692AE1B44,551 is specified exclusively for +5 V ±10% operation. Its DC electrical characteristics - including VIH (2.0 V min), VOL (0.4 V max), and ICC (10 mA typical) - are validated only at VCC = 5 V. Operation at 3.3 V is outside the Absolute Maximum Ratings and may result in undefined behavior, register corruption, or failure to meet timing specifications.
How many interrupt sources does SCC2692AE1B44,551 support?
The SCC2692AE1B44,551 supports eight distinct maskable interrupt sources routed to the single active-low INTRN output: receiver ready, transmitter ready, receiver full, break detect, framing error, parity error, overrun error, and counter/timer event. Additionally, outputs OP3–OP7 can be individually configured as discrete open-drain interrupt signals - providing up to six dedicated interrupt lines alongside INTRN.
Is SCC2692AE1B44,551 pin-compatible with the SCN2681?
Yes, the SCC2692AE1B44,551 is explicitly stated in the Philips product specification to be compatible with the SCN2681. This includes identical pin functions, register mapping, and electrical interface behavior. However, the SCC2692 adds enhancements including quadruple receiver buffering, expanded baud rate options, and improved multidrop mode - all implemented without altering the pinout or memory-mapped I/O protocol.
SCC2692AE1B44,551 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 44-QFP
- Series:
- -
- Packaging:
- Tray
- Product Status:
- Obsolete
- Features:
- Configurable GPIO, Internal Oscillator, Timer/Counter
- Number of Channels:
- 2, DUART
- FIFO's:
- -
- Protocol:
- -
- Data Rate (Max):
- 1Mbps
- Voltage - Supply:
- 5V
- With Auto Flow Control:
- Yes
- With IrDA Encoder/Decoder:
- -
- With False Start Bit Detection:
- Yes
- With Modem Control:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 44-PQFP (10x10)
SCC2692AE1B44,551 FAQ
1.How can I place an order for SCC2692AE1B44,551 through Aetrix?
Please submit a Request for Quotation (RFQ) for SCC2692AE1B44,551 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SCC2692AE1B44,551 reliable?
The price and inventory of SCC2692AE1B44,551 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SCC2692AE1B44,551 is usually 5 days.
3.What payment methods are accepted for SCC2692AE1B44,551?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SCC2692AE1B44,551 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SCC2692AE1B44,551?
SCC2692AE1B44,551 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SCC2692AE1B44,551 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SCC2692AE1B44,551?
For technical support, including SCC2692AE1B44,551 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SCC2692AE1B44,551 requirements.
6.How does Aetrix verify that SCC2692AE1B44,551 is sourced from the original manufacturer or authorized distributors?
All SCC2692AE1B44,551 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SCC2692AE1B44,551 meets industry standards.
7.What is the process for return or replacement of SCC2692AE1B44,551?
All SCC2692AE1B44,551 units undergo pre-shipment inspection (PSI). If there is an issue with SCC2692AE1B44,551, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SCC2692AE1B44,551 part is unused and in its original packaging.
Return procedure for SCC2692AE1B44,551:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SCC2692AE1B44,551 Tags

-
SC16IS741AIPWJ
NXP Semiconductors

-
TL16C550CPTR
Texas Instruments

-
TL16C550CIPTR
Texas Instruments

-
SC16C752BIB48,128
NXP Semiconductors

-
ST16C2550CQ48-F
MaxLinear, Inc.

-
ST16C2550CJ44-F
MaxLinear, Inc.

-
ST16C2552CJ44-F
MaxLinear, Inc.

-
ST16C1550IQ48-F
MaxLinear, Inc.

-
ST16C2550IQ48-F
MaxLinear, Inc.

-
ST16C554DIQ64-F
MaxLinear, Inc.

-
ST16C554DCQ64-F
MaxLinear, Inc.
-
XR17V352IB113-F
MaxLinear, Inc.
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

