NXP Semiconductors SCC68681E1A44,529
- Part No.:
- SCC68681E1A44,529
- Manufacturer:
- NXP Semiconductors
- Package:
- 44-LCC (J-Lead)
- Datasheet:
-
SCC68681E1A44,529.pdf
- Description:
- IC DUART 1MBPS 44PLCC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SCC68681E1A44 from NXP Semiconductors (formerly Philips Semiconductors) is a dual-channel CMOS universal asynchronous receiver/transmitter (DUART) in PLCC44 package, supporting independent full-duplex serial communication on Channels A and B with programmable 5–8 data bits, 1/1.5/2 stop bits, odd/even/no parity, and up to 115.2 kbaud. It integrates a 16-bit counter/timer, quadruple-buffered receivers, and multipurpose 6-bit input/8-bit output ports - deployed in industrial control backplanes and legacy embedded systems requiring robust RS-232/RS-422 interface management.
For engineers reviewing the SCC68681E1A44 datasheet, SCC68681E1A44 pinout, SCC68681E1A44 application, or SCC68681E1A44 equivalent, key selection criteria include independent baud rate programming per channel, hardware flow control via RTS/CTS, crystal oscillator integration (X1/X2), 44-pin PLCC mechanical compatibility, and interrupt vectoring support for S68000-family microprocessors.
Technical Context
The SCC68681E1A44 implements two fully independent UART channels sharing a common 8-bit bidirectional data bus (D0–D7), address decoding (A1–A4), and interrupt architecture. Each channel features separate mode registers (MR1/MR2), status registers (SRA/SRB), and command registers (CRA/CRB), enabling asymmetric configuration - e.g., Channel A at 9600 baud with 8N1 while Channel B runs at 38.4 kbaud with 7E2.
Its timing subsystem includes an on-chip crystal oscillator (X1/CLK, X2), a baud rate generator producing 22 fixed rates (50–115.2 kbaud), and a 16-bit counter/timer usable as timer, counter, or timeout monitor. Clock selection logic allows each receiver and transmitter to source timing independently from BRG, counter/timer, or external 1×/16× clocks - critical for multidrop wake-up and dual-speed terminal clustering.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Function | Dual full-duplex asynchronous receiver/transmitter (DUART) with independent channel control |
| Supply Voltage | +5 V ±10% - supports industrial temperature range (–40 °C to +85 °C) |
| Data Format | 5–8 data bits, odd/even/no/force parity, 1/1.5/2 stop bits - programmable per channel in 1/16-bit increments |
| Baud Rate Range | 50 to 115.2 kbaud - 22 fixed rates plus user-defined non-standard rates via 16-bit counter/timer |
| Receiver Buffering | Quadruple-buffered FIFO (3-character depth + shift register) - reduces overrun risk and interrupt overhead |
| Interrupt Architecture | Single active-low INTRN output with 8 maskable sources; interrupt vector output on IACKN; up to six wire-ORable discrete interrupt outputs via OP3–OP7 |
| Package | PLCC44 (SOT187-2) - 44-lead plastic leaded chip carrier with J-leads, suitable for through-hole or surface-mount reflow |
Pinout & Package
SCC68681E1A44 is housed in a 44-lead PLCC (SOT187-2) package with J-type leads, designed for industrial-grade thermal and mechanical reliability. Pin 44 is VCC (+5 V), Pin 22 is GND, and Pins 32 (X1/CLK) and 33 (X2) support direct crystal connection (e.g., 3.6864 MHz) or external clock input.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 39 (CSN) | Chip Select | Active-low enable for data transfers on D0–D7; places bus in high-impedance state when deasserted |
| 9 (R/WN) | Read/Write Control | High = read cycle, low = write cycle - synchronized with CSN and DTACKN for S68000 bus timing compliance |
| 35 (RxDA), 11 (RxDB) | Channel A/B Serial Input | Asynchronous receive inputs sampled on rising edge of internal 16× clock; support external clocking via IP4/IP5 |
| 33 (TxDA), 13 (TxDB) | Channel A/B Serial Output | Transmit outputs held HIGH (mark) when idle/disabled; support auto RS-485 turn-around via OP0/OP1 |
| 38 (RESETN) | Master Reset | Active-low asynchronous reset clearing SRA/SRB/IMR/ISR/OPR, initializing IVR to 0xF, and halting counter/timer |
| 24 (INTRN) | Interrupt Request | Open-drain active-low output asserting on any of eight maskable conditions - requires external pull-up |
| 41 (IACKN) | Interrupt Acknowledge | Active-low CPU signal triggering DUART to place interrupt vector on D0–D7 and assert DTACKN |
| 32 (X1/CLK), 33 (X2) | Clock Input | Crystal oscillator terminals - accept 3.6864 MHz crystal or external clock; X2 left unconnected if external clock used |
Key Features
| Feature | Design Value |
|---|---|
| Independent channel baud rate selection | Each receiver and transmitter can select timing from 22 fixed rates, counter/timer-derived rates, or external 1×/16× clocks - enables dual-speed operation in clustered terminals |
| Quadruple-buffered receiver architecture | 3-deep FIFO + shift register minimizes overrun during burst reception and reduces CPU polling frequency in interrupt-driven systems |
| Hardware flow control with RTS/CTS | OP0/OP1 (RTSAN/RTSBN) and IP0/IP1 (CTSAN/CTSBN) support automatic RTS deactivation when FIFO fills - prevents data loss without software intervention |
| Multidrop wake-up mode | MR1A[4:3]/MR1B[4:3] = 11 configures receiver to detect address-tagged characters (A/D bit = 1) while disabled - wakes CPU only on targeted commands |
| Programmable 6-bit input port with change detection | IP0–IP5 provide general-purpose inputs with 100 kΩ internal pull-ups and four change-of-state detectors - enables hardware event logging without CPU polling |
| Auto RS-485 turn-around on OP0/OP1 | Output Port Configuration Register (OPCR) enables automatic RTS assertion/retraction synchronized to TxDA/TxDB activity - eliminates external transceiver control logic |
Applications
| Industrial Backplane Communication | Legacy Terminal Server Interface |
|---|---|
Use Scenario: Connecting PLC I/O modules to a central controller over long-haul RS-422 links in factory automation cabinets. IC Role / Device Role / Timing Role: SCC68681E1A44 acts as dual-channel line interface controller, managing differential transmit/receive paths with independent 19.2 kbaud timing and hardware RTS/CTS handshaking. Use Value: Quadruple buffering and multidrop wake-up reduce bus arbitration latency; PLCC44 package ensures mechanical stability in vibration-prone enclosures. | Use Scenario: Enabling concurrent serial console access to multiple legacy Unix workstations via a single terminal server card. IC Role / Device Role / Timing Role: SCC68681E1A44 serves as dual UART core, assigning Channel A to primary console (9600 baud, 8N1) and Channel B to secondary debug port (38.4 kbaud, 7E2). Use Value: Independent baud rate generators eliminate need for external clock dividers; interrupt vectoring simplifies ISR dispatch in real-time OS environments. |
| Medical Device Data Logging | Avionics Maintenance Port |
Use Scenario: Aggregating diagnostic telemetry from ECG, SpO₂, and NIBP sensors into a centralized patient monitor with isolated RS-232 outputs. IC Role / Device Role / Timing Role: SCC68681E1A44 operates as dual asynchronous bridge, using Channel A for sensor polling (115.2 kbaud) and Channel B for archival log upload (57.6 kbaud). Use Value: On-chip crystal oscillator (X1/X2) removes external timing components; industrial temp rating (–40 °C to +85 °C) sustains operation in uncontrolled clinical environments. | Use Scenario: Providing ground-crew maintenance access to flight control computers via ARINC 429-to-RS-232 protocol converters in aircraft avionics bays. IC Role / Device Role / Timing Role: SCC68681E1A44 functions as dual UART interface, with Channel A handling maintenance command streams and Channel B relaying system health reports. Use Value: False start-bit detection and break generation ensure robust command framing under EMI-heavy conditions; RESETN pin enables cold-start recovery after power cycling. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual UART applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SCC68681C1A44 | Same die, commercial temperature range (0 °C to +70 °C); identical pinout and electrical specs except VCC tolerance (±5% vs ±10%) | Not rated for industrial ambient extremes; unsuitable for outdoor or engine-bay deployments | Select SCC68681C1A44 only for cost-sensitive commercial equipment operating in climate-controlled environments. |
| TL16C550CIPN | Single-channel UART with 16-byte FIFO, TI-enhanced register set, and +3.3 V / +5 V dual-supply support - no counter/timer or multidrop mode | Lacks dual-channel integration, hardware flow control granularity, and wake-up capability required for terminal clustering | Choose TL16C550CIPN when upgrading legacy single-UART designs with deeper FIFOs but no need for dual-channel synchronization. |
Compared with SCC68681C1A44, the SCC68681E1A44 provides guaranteed operation across –40 °C to +85 °C and wider supply tolerance, making it essential for ruggedized systems; versus TL16C550CIPN, it delivers true dual-channel independence, integrated counter/timer, and multidrop wake-up - capabilities absent in single-UART alternatives.
Availability
SCC68681E1A44 is available at Aetrix Electronics and suitable for industrial backplane communication, legacy terminal server interface, medical device data logging, and avionics maintenance port applications requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for SCC68681E1A44 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors, headquartered in Eindhoven, Netherlands, develops high-performance mixed-signal ICs for automotive, industrial, and communication infrastructure markets, with legacy roots in Philips Semiconductors' MOS-LSI division.
The SCC68681E1A44 belongs to NXP's legacy communications interface product line, originally architected for S68000-family microprocessor systems requiring dual-channel asynchronous serial connectivity with minimal external components and deterministic interrupt response.
FAQ
What is the maximum supported baud rate for SCC68681E1A44?
The SCC68681E1A44 supports a maximum data transfer rate of 115.2 kbaud using its internal baud rate generator. This applies to both Channel A and Channel B independently. The device also permits non-standard rates up to 115.2 kbaud via its 16-bit programmable counter/timer, and achieves 1 MB/sec parallel bus throughput (1× clock mode) or 125 kB/sec (16× clock mode) on the D0–D7 data bus. All timing assumes a nominal 3.6864 MHz crystal on X1/CLK.
Does SCC68681E1A44 include an integrated crystal oscillator?
Yes, the SCC68681E1A44 includes an on-chip crystal oscillator circuit. Pins 32 (X1/CLK) and 33 (X2) are dedicated to connecting a 3.6864 MHz crystal; alternatively, an external clock signal may be applied to X1/CLK while leaving X2 unconnected. The oscillator feeds the baud rate generator, counter/timer, and all internal timing blocks - eliminating the need for external oscillator components in most designs.
How does hardware flow control work on SCC68681E1A44?
Hardware flow control on the SCC68681E1A44 uses OP0/OP1 (RTSAN/RTSBN) and IP0/IP1 (CTSAN/CTSBN). When enabled via mode registers, the DUART automatically asserts RTS upon detecting a valid start bit and deasserts it when the 3-character receiver FIFO reaches capacity. CTS inputs gate transmission: if CTSN goes HIGH mid-transmission, the current character completes but TxDA remains in mark state until CTSN returns LOW. This prevents buffer overrun without CPU intervention.
Can SCC68681E1A44 operate in multidrop networks?
Yes, the SCC68681E1A44 supports multidrop wake-up mode via MR1A[4:3] or MR1B[4:3] = 11. In this mode, the receiver monitors the serial stream continuously - even when disabled - and asserts RxRDY only when an address-tagged character (A/D bit = 1) is received. This allows a master station to broadcast addresses to multiple slaves, waking only the intended target. The A/D bit polarity is programmable per channel via MR1A[2]/MR1B[2].
What package type is used for SCC68681E1A44?
The SCC68681E1A44 uses a 44-lead plastic leaded chip carrier (PLCC) package, designated SOT187-2. It features J-shaped leads for surface-mount assembly and is rated for industrial temperature operation (–40 °C to +85 °C). This package is mechanically and electrically identical to the SCC68681C1A44 variant, differing only in temperature specification and supply voltage tolerance.
SCC68681E1A44,529 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 44-LCC (J-Lead)
- Series:
- -
- Packaging:
- Tube
- Product Status:
- Obsolete
- Features:
- Configurable GPIO, Internal Oscillator, Timer/Counter
- Number of Channels:
- 2, DUART
- FIFO's:
- -
- Protocol:
- -
- Data Rate (Max):
- 1Mbps
- Voltage - Supply:
- 5V
- With Auto Flow Control:
- Yes
- With IrDA Encoder/Decoder:
- -
- With False Start Bit Detection:
- Yes
- With Modem Control:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 44-PLCC (16.59x16.59)
SCC68681E1A44,529 FAQ
1.How can I place an order for SCC68681E1A44,529 through Aetrix?
Please submit a Request for Quotation (RFQ) for SCC68681E1A44,529 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SCC68681E1A44,529 reliable?
The price and inventory of SCC68681E1A44,529 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SCC68681E1A44,529 is usually 5 days.
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4.How is shipping managed for SCC68681E1A44,529?
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Once your SCC68681E1A44,529 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SCC68681E1A44,529?
For technical support, including SCC68681E1A44,529 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SCC68681E1A44,529 requirements.
6.How does Aetrix verify that SCC68681E1A44,529 is sourced from the original manufacturer or authorized distributors?
All SCC68681E1A44,529 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SCC68681E1A44,529 meets industry standards.
7.What is the process for return or replacement of SCC68681E1A44,529?
All SCC68681E1A44,529 units undergo pre-shipment inspection (PSI). If there is an issue with SCC68681E1A44,529, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SCC68681E1A44,529 part is unused and in its original packaging.
Return procedure for SCC68681E1A44,529:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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