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NXP Semiconductors SCC68681E1N40,112
- Part No.:
- SCC68681E1N40,112
- Manufacturer:
- NXP Semiconductors
- Package:
- 40-DIP (0.600", 15.24mm)
- Datasheet:
-
SCC68681E1N40,112.pdf
- Description:
- IC DUART 1MBPS 40DIP
- Quantity:
- Payment:
- Shipping:
Inventory:2,140
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Product details
Overview
SCC68681E1N40 from NXP Semiconductors (formerly Philips Semiconductors) is a dual-channel CMOS universal asynchronous receiver/transmitter (DUART) in a 40-pin DIP package, supporting independent full-duplex serial communication at up to 115.2 kbaud per channel, with quadruple-receiver buffering, programmable data format (5–8 bits, parity, 1/1.5/2 stop bits), and integrated 16-bit counter/timer - used in industrial control backplanes and legacy embedded systems requiring robust RS-232/RS-422 interface management.
For engineers reviewing the SCC68681E1N40 datasheet, SCC68681E1N40 pinout, SCC68681E1N40 application, or SCC68681E1N40 equivalent, key selection considerations include its dual-channel interrupt-driven UART architecture, independent baud rate generation per channel (crystal or external clock), 6-bit input/8-bit output port configurability, industrial temperature range (–40 °C to +85 °C), and S68000 bus compatibility for microprocessor interfacing.
Technical Context
The SCC68681E1N40 implements two independent UART channels (A and B), each with fully programmable framing (data bits, parity type, stop bits), separate receiver/transmitter baud rate selection from 18 fixed rates or user-defined via 16-bit counter/timer, and quadruple-buffered receive FIFOs to prevent overrun in high-interrupt-latency systems. Its timing subsystem integrates an on-chip crystal oscillator (3.6864 MHz nominal), selectable clock sources (X1/CLK or external), and four clock selectors enabling asymmetric Rx/Tx clocking.
Interrupt handling uses a single active-low open-drain INTRN output with eight maskable conditions, supported by Interrupt Mask Register (IMR), Interrupt Status Register (ISR), and Interrupt Vector Register (IVR); additionally, outputs OP3–OP7 can be configured as discrete wire-ORable interrupt signals for TxRDY, RxRDY, or C/T events - enabling flexible system-level event prioritization without external logic.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Channels | Dual independent full-duplex UARTs (Channel A and Channel B) |
| Max Baud Rate | 115.2 kbaud per channel - supports standard modem and industrial serial protocols |
| Receiver Buffer Depth | Quadruple-buffered FIFO (3-character depth + shift register) - reduces CPU interrupt overhead and prevents overrun at sustained 9600+ baud |
| Data Format | 5–8 data bits, odd/even/no/force parity, 1/1.5/2 stop bits - enables interoperability with legacy teletype, terminal, and protocol-specific devices |
| Counter/Timer | 16-bit programmable down-counter - generates custom baud clocks, time delays, or timeout detection for flow control |
| Operating Voltage | +5 V ±10% - compatible with industrial 5 V logic rails and tolerant of supply ripple |
| Temperature Range | –40 °C to +85 °C - qualified for extended industrial environments including factory automation and transportation systems |
| Package | 40-pin plastic dual in-line package (DIP40, 600 mil) - through-hole mounting for high-reliability board assembly and long-lifecycle designs |
Pinout & Package
SCC68681E1N40 is housed in a 40-pin plastic dual in-line package (DIP40, 600 mil width), with 0.1″ lead pitch and through-hole mounting. Pin 1 is located at the left end of the top row (notch-down orientation). Power (VCC, Pin 40) and ground (GND, Pin 20) are positioned for low-noise decoupling. All I/O pins are TTL-compatible and 3-state controlled.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| Pin 1 (A1) | Address Input | Selects internal register address during CPU read/write cycles - part of 4-bit address bus (A1–A4) for accessing 16 registers |
| Pin 8 (R/WN) | Read/Write Control | Active-low signal indicating CPU read (HIGH) or write (LOW) operation - synchronizes data transfer with CSN and DTACKN |
| Pin 35 (RxDA) | Channel A Serial Input | Asynchronous serial data input for Channel A - sampled on rising edge of internal 16× clock; 'mark' = HIGH, 'space' = LOW |
| Pin 33 (TxDA) | Channel A Serial Output | Asynchronous serial data output for Channel A - transmits LSB-first with programmable start/stop/parity; held HIGH when idle |
| Pin 36 (X1/CLK) | Clock Input | Primary timing source - accepts either 3.6864 MHz crystal or external clock; drives baud generator, counter/timer, and internal logic |
| Pin 38 (RESETN) | Reset Input | Active-low asynchronous reset - clears registers, stops counter/timer, initializes IVR to 0Fh, and sets OP0–OP7 HIGH |
| Pin 21 (INTRN) | Interrupt Output | Open-drain active-low interrupt request - asserted when any of eight maskable conditions occur; requires external pull-up |
| Pin 32 (OP0) | Output Port Bit 0 | Programmable general-purpose output or Channel A RTS (RTSAN) - auto-deactivates on Rx/Tx completion when configured for flow control |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent baud rate generators | Each channel selects from 22 fixed rates (50–115.2 kbaud) or user-defined rate via 16-bit counter/timer - enables asymmetric link speeds (e.g., host-to-terminal vs. terminal-to-host) |
| Quadruple-buffered receiver FIFO | 3-character deep FIFO + shift register - eliminates character loss during CPU servicing delays in interrupt-driven systems |
| Multi-function I/O ports | 6-bit input port (IP0–IP5) with change-of-state detection and 8-bit output port (OP0–OP7) with individual bit set/reset - replaces discrete glue logic for status signaling and handshaking |
| Automatic hardware flow control | RTS/CTS handshake with auto-deactivation on FIFO full - prevents receiver overrun without software polling or timer-based throttling |
| Multidrop wake-up mode | Address/data bit tagging (MR1x[2]) and automatic RxRDY assertion on address match - reduces power and CPU load in multi-node bus systems |
| Versatile interrupt architecture | Single INTRN output with vector capability plus six configurable OP pins for discrete interrupts - simplifies priority arbitration in resource-constrained microcontroller systems |
Applications
| Industrial PLC Backplane Interface | Legacy Terminal Server Management |
|---|---|
Use Scenario: Connecting multiple RS-232 field devices (sensors, HMIs, actuators) to a central PLC CPU via a shared backplane bus. IC Role / Device Role / Timing Role: Dual UART bridge providing isolated, interrupt-driven serial channels with independent baud rates and hardware flow control. Use Value: Eliminates need for external bus transceivers and discrete flow-control logic; quadruple buffering ensures no data loss during scan-cycle jitter in deterministic control loops. | Use Scenario: Managing concurrent dial-up connections from dumb terminals in a centralized UNIX terminal server rack. IC Role / Device Role / Timing Role: Dual-channel serial controller handling simultaneous login sessions, with per-port baud rate flexibility and multidrop wake-up for address-directed command routing. Use Value: Reduces CPU interrupt load via Rx FIFO buffering and discrete OPx interrupt outputs - enabling stable 16-session throughput on 80386-class processors. |
| Avionics Maintenance Data Link | Ruggedized Point-of-Sale Terminal |
Use Scenario: Bidirectional diagnostic data exchange between aircraft avionics modules and ground maintenance laptops using ARINC 429-compatible physical layer adapters. IC Role / Device Role / Timing Role: Robust UART interface with industrial temp rating, crystal-based timing stability, and false-start-bit rejection for noisy aircraft electrical environments. Use Value: Maintains reliable 19.2 kbaud link integrity despite EMI transients; on-chip oscillator eliminates external crystal layout sensitivity in compact line-replaceable units. | Use Scenario: Integrating magnetic stripe reader, receipt printer, and cash drawer control into a single-board POS terminal operating in retail environments with wide ambient temperature swings. IC Role / Device Role / Timing Role: Multi-I/O serial hub managing three asynchronous peripherals via dedicated UART channels and programmable OP/TP ports. Use Value: Replaces three discrete UART ICs and discrete I/O expanders - reducing BOM count, PCB area, and qualification effort for UL/CE safety certification. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual UART applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SCC68681E1A44 | Same die, PLCC44 package (surface-mount), identical electrical specs and register map | Requires rework of PCB layout for surface-mount assembly; no change in firmware or timing behavior | Select when space-constrained designs favor SMT over through-hole or require automated placement |
| TL16C550CP | Single-channel UART with 16-byte FIFO, TI-compatible register set, +5 V only, no counter/timer or multidrop mode | Lacks dual-channel capability and asymmetric baud control; requires two devices for equivalent functionality | Select only if legacy BIOS/OS drivers mandate TI 16550 compatibility and dual-channel integration is not required |
Compared with SCC68681E1N40, the SCC68681E1A44 offers identical functionality in a space-saving PLCC package but demands PCB redesign, while the TL16C550CP provides industry-standard register compatibility at the cost of channel count, advanced flow control, and integrated timing - making it suitable only for single-link upgrades where firmware reuse outweighs hardware consolidation.
Availability
SCC68681E1N40 is available at Aetrix Electronics and suitable for industrial PLC backplanes, legacy terminal servers, avionics maintenance interfaces, and ruggedized point-of-sale terminals requiring stable component supply across extended product lifecycles.
Supply support for SCC68681E1N40 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT applications, with roots in Philips Semiconductors' analog and mixed-signal heritage.
The SCC68681 belongs to NXP's legacy communications interface product line, designed specifically for high-reliability embedded systems requiring dual asynchronous serial channels with deterministic interrupt response and long-term obsolescence resilience.
FAQ
What is the maximum supported baud rate for each channel of the SCC68681E1N40?
The SCC68681E1N40 supports a maximum baud rate of 115.2 kbaud per channel. This is achieved using the internal baud rate generator with a 3.6864 MHz crystal reference or an equivalent external clock. The device also allows non-standard rates up to this limit via its programmable 16-bit counter/timer, enabling precise matching to proprietary or legacy protocol requirements. Each channel's receiver and transmitter can be independently configured for different rates.
Does the SCC68681E1N40 support hardware flow control, and how is it implemented?
Yes, the SCC68681E1N40 supports automatic hardware flow control using RTS/CTS signaling. When configured via the mode registers, OP0 (for Channel A) or OP1 (for Channel B) functions as an active-low RTS output that deactivates automatically when the corresponding receiver FIFO reaches capacity. This signal can be connected directly to the CTS input of a remote transmitter to pause data flow - preventing receiver overrun without CPU intervention or software polling.
Can the SCC68681E1N40 operate without an external crystal?
Yes, the SCC68681E1N40 can operate without an external crystal by using an external clock signal applied to the X1/CLK pin (Pin 36). The device accepts a square-wave clock input within specified voltage and frequency limits (typically 3.6864 MHz for standard baud rates). In this configuration, X2 (Pin 37) should remain unconnected. The internal oscillator circuitry is bypassed, and all timing-including baud generation and counter/timer operation-derives from the external clock source.
How does the receiver FIFO in the SCC68681E1N40 prevent data loss during high-speed operation?
The SCC68681E1N40 features a quadruple-buffered receiver path consisting of a 3-character deep FIFO plus the receive shift register. When enabled, this structure allows up to three complete characters to be stored while the CPU services prior interrupts. The RxRDY flag asserts as soon as one character is available, and FFULL asserts when the FIFO is full - both conditionally triggerable as interrupts. This design minimizes the risk of overrun even under moderate CPU latency, especially critical in real-time industrial control applications.
Is the SCC68681E1N40 pin-compatible with other members of the SCC68681 family?
Yes, the SCC68681E1N40 is pin-compatible with the SCC68681C1N40 (commercial grade) and shares identical pinout, register mapping, and electrical behavior with the PLCC-packaged variants (SCC68681E1A44 and SCC68681C1A44), differing only in temperature range and package type. Firmware and hardware designs developed for any SCC68681 DIP40 variant can be reused without modification - making it straightforward to migrate between commercial and industrial grades or between through-hole and surface-mount assembly.
SCC68681E1N40,112 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 40-DIP (0.600", 15.24mm)
- Series:
- -
- Packaging:
- Tube
- Product Status:
- Obsolete
- Features:
- Configurable GPIO, Internal Oscillator, Timer/Counter
- Number of Channels:
- 2, DUART
- FIFO's:
- -
- Protocol:
- -
- Data Rate (Max):
- 1Mbps
- Voltage - Supply:
- 5V
- With Auto Flow Control:
- Yes
- With IrDA Encoder/Decoder:
- -
- With False Start Bit Detection:
- Yes
- With Modem Control:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 40-DIP
SCC68681E1N40,112 FAQ
1.How can I place an order for SCC68681E1N40,112 through Aetrix?
Please submit a Request for Quotation (RFQ) for SCC68681E1N40,112 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SCC68681E1N40,112 reliable?
The price and inventory of SCC68681E1N40,112 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SCC68681E1N40,112 is usually 5 days.
3.What payment methods are accepted for SCC68681E1N40,112?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SCC68681E1N40,112 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SCC68681E1N40,112?
SCC68681E1N40,112 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SCC68681E1N40,112 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SCC68681E1N40,112?
For technical support, including SCC68681E1N40,112 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SCC68681E1N40,112 requirements.
6.How does Aetrix verify that SCC68681E1N40,112 is sourced from the original manufacturer or authorized distributors?
All SCC68681E1N40,112 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SCC68681E1N40,112 meets industry standards.
7.What is the process for return or replacement of SCC68681E1N40,112?
All SCC68681E1N40,112 units undergo pre-shipment inspection (PSI). If there is an issue with SCC68681E1N40,112, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SCC68681E1N40,112 part is unused and in its original packaging.
Return procedure for SCC68681E1N40,112:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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