My Inquiry
My Account
NXP Semiconductors SCC68692C1N40,602
- Part No.:
- SCC68692C1N40,602
- Manufacturer:
- NXP Semiconductors
- Package:
- 40-DIP (0.600", 15.24mm)
- Datasheet:
-
SCC68692C1N40,602.pdf
- Description:
- IC DUART 1MBPS 40DIP
- Quantity:
- Payment:
- Shipping:
Inventory:2,814
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SCC68692C1N40,602 from NXP Semiconductors (formerly Philips Semiconductors) is a dual-channel CMOS-LSI universal asynchronous receiver/transmitter (DUART) in a 40-pin DIP package, supporting independent full-duplex serial communication on Channels A and B with programmable baud rates up to 115.2 kbaud, quadruple receiver buffering, and TTL-compatible +5 V operation for industrial terminal and embedded control systems.
For engineers reviewing the SCC68692C1N40,602 datasheet, SCC68692C1N40,602 pinout, SCC68692C1N40,602 application, or SCC68692C1N40,602 equivalent, key selection considerations include independent channel baud rate configuration (1X/16X clock options), receiver timeout and multidrop wake-up mode support, 6-bit input port with change-of-state detection, and 8-bit output port with individual bit set/reset capability for status/interrupt signaling.
Technical Context
The SCC68692C1N40,602 implements two independent UART channels sharing a common S68000-bus-compatible parallel interface, each with fully programmable data format (5–8 data bits, odd/even/no/force parity, 1/1.5/2 stop bits), separate receiver/transmitter clock sources (crystal oscillator, counter/timer, or external 1X/16X clocks), and integrated 16-bit counter/timer supporting timer, counter, and receiver timeout modes.
Its interrupt architecture features a single active-low open-drain INTRN output with eight maskable conditions, plus optional discrete interrupt outputs on OP3–OP7, while the on-chip crystal oscillator accepts a 3.6864 MHz crystal at X1/CLK and X2 pins - enabling self-contained timing without external clock generation circuitry.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Baud Rates | Up to 115.2 kbaud per channel; selectable from 22 fixed rates or user-defined via 16-bit counter/timer. |
| Data Format | 5–8 data bits, odd/even/no/force parity, 1/1.5/2 stop bits - programmable per channel in 1/16-bit increments. |
| Receiver Buffering | Quadruple-buffered RHR per channel - reduces overrun risk and interrupt overhead in high-throughput polled systems. |
| Power Supply | +5 V ±10 % - TTL-compatible operation across commercial (0 to +70 °C) and industrial (–40 to +85 °C) temperature ranges. |
| Crystal Oscillator | On-chip oscillator supports 3.6864 MHz crystal (X1/CLK and X2); external clock input also accepted at X1/CLK. |
| Interrupt System | Single INTRN output with eight maskable sources; OP3–OP7 configurable as six wire-ORable discrete interrupt outputs. |
| Input/Output Ports | 6-bit multipurpose input port (IP0–IP5) with change-of-state detection on four inputs; 8-bit output port (OP0–OP7) with individual bit set/reset. |
Pinout & Package
SCC68692C1N40,602 is housed in a 40-pin plastic dual in-line package (DIP), 600 mils wide (SOT129-1), with 0.1-inch lead pitch and through-hole mounting. Pin 1 is index-corner marked; pins 12 and 23 are NC (no connect); pin 20 is GND; pin 40 is VCC.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1,2,5,6 (A1–A4) | Address Inputs | Select internal registers/ports during CPU read/write cycles; decode 16 addresses including THR, RHR, CSR, IMR, ISR, OPR, IPCR, etc. |
| 7,4,2,36,39,38 (IP0–IP5) | Input Port Pins | General-purpose inputs or dedicated functions: CTSAN/CTSBN, RxCA/RxCB, TxCA/TxCB, CTCLK; all feature internal ~1–4 µA pull-up resistors. |
| 29,12,28,13,27,14,26,15 (OP0–OP7) | Output Port Pins | Programmable as general-purpose outputs or functional signals: RTSAN/RTSBN, TxRDYAN/TxRDYBN, RxRDYAN/FFULLAN, counter/timer output, clock outputs. |
| 31,10 (RxDA, RxDB) | Receiver Inputs | Asynchronous serial data inputs for Channel A and B; sampled on rising edge of 1X clock or at center of bit time in 16X mode. |
| 30,11 (TxDA, TxDB) | Transmitter Outputs | Asynchronous serial data outputs; held HIGH ("mark") when idle, disabled, or in loopback; LSB-first transmission with auto-inserted start/stop/parity bits. |
| 8 (R/WN), 35 (CSN), 9 (DTACKN), 21 (INTRN), 37 (IACKN) | Bus Control Signals | TTL-compatible 68000-family bus interface: active-low read/write strobe, chip select, data transfer acknowledge, interrupt request, and acknowledge. |
| 32 (X1/CLK), 33 (X2) | Clock Inputs | Crystal oscillator terminals; accept 3.6864 MHz crystal or external clock; X1/CLK also serves as clock input for external timing modes. |
| 34 (RESETN) | Reset Input | Active-low hardware reset: clears SRA/SRB, IMR/ISR, OPR/OPCR, stops counter/timer, initializes IVR to 0xF, sets OP0–OP7 HIGH. |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent UART channels | Enables simultaneous serial links (e.g., host console + peripheral modem) without external multiplexing or software arbitration. |
| Quadruple receiver buffering per channel | Reduces CPU polling frequency and minimizes data loss in bursty traffic or interrupt-latency-sensitive applications. |
| Programmable multidrop/wake-up mode | Supports 9-bit addressing for clustered terminal systems - allows selective channel activation without continuous polling. |
| 6-bit input port with change-of-state detection | Monitors up to four external signals (e.g., pushbuttons, limit switches) and generates interrupts on transitions - eliminates need for external debouncing logic. |
| 8-bit output port with individual bit control | Permits fine-grained control of discrete I/O (e.g., LED indicators, relay drivers) or mapping of internal status (TxRDY, RxRDY) to dedicated pins. |
| Receiver timeout and automatic break detection | Identifies idle line conditions and mid-character breaks - critical for robust protocol framing in RS-232/RS-485 multi-drop networks. |
Applications
| Industrial Terminal Systems | Embedded Controller Communication |
|---|---|
|
Use Scenario: Multi-terminal point-of-sale (POS) or HMI system where one master controller communicates with multiple remote displays/keypads over RS-232/422 links. IC Role / Device Role / Timing Role: DUART provides two independent serial interfaces - Channel A handles local debug console; Channel B manages remote terminal polling in multidrop mode with 9-bit address wake-up. Use Value: Eliminates need for two discrete UARTs or external address decoding logic; quadruple buffering ensures reliable reception under variable latency conditions. |
Use Scenario: Programmable logic controller (PLC) backplane requiring isolated serial communication with I/O modules and human-machine interface units. IC Role / Device Role / Timing Role: SCC68692C1N40,602 acts as the primary serial interface IC, interfacing microprocessor bus to dual RS-485 transceivers with independent baud rate control per link. Use Value: Independent receiver/transmitter clock selection enables mismatched link speeds (e.g., 9600 bps to I/O module, 38.4 kbps to HMI), reducing firmware complexity. |
| Legacy Equipment Emulation | Test & Measurement Instrumentation |
|
Use Scenario: Retrofit of aging test equipment requiring replacement of obsolete SCN68681-based serial interface with pin-compatible modern alternative. IC Role / Device Role / Timing Role: Drop-in replacement DUART maintaining identical S68000 bus timing, register map, and interrupt behavior - preserving legacy firmware compatibility. Use Value: Enables continued production of fielded instruments without PCB redesign; same 40-pin DIP footprint and electrical characteristics ensure mechanical and thermal drop-in fit. |
Use Scenario: Automated calibration station where a central PC controls multiple instruments via RS-232, requiring reliable low-latency command/response handshaking. IC Role / Device Role / Timing Role: SCC68692C1N40,602 serves as the serial interface engine in the instrument's microcontroller subsystem, using OP0–OP7 for hardware flow control (RTS/CTS) and status signaling. Use Value: Hardware-managed RTS/CTS on OP0 (RTSAN) and IP0 (CTSAN) offloads flow control from CPU, ensuring deterministic response to high-speed command bursts. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual UART applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SCN68681B1N40 | Legacy predecessor; identical pinout and register set but lacks receiver timeout mode and multidrop wake-up capability. | Not suitable for new designs requiring robust idle-line detection or 9-bit addressable multidrop networks. | Select SCC68692C1N40,602 when receiver timeout, false start bit detection, or enhanced multidrop support is required. |
| MAX3100CEE+ | SPI-interface UART with integrated RS-232 level shifters; 3.3 V only; no parallel bus interface or counter/timer. | Requires SPI host and level translation; unsuitable for 68000-family bus systems or applications needing independent clock sources per channel. | Choose MAX3100CEE+ only for compact, low-voltage, SPI-based designs where parallel bus integration is not needed. |
Compared with SCN68681B1N40, the SCC68692C1N40,602 adds receiver timeout and multidrop wake-up - critical for power-efficient remote terminal polling. Against MAX3100CEE+, it retains native 68000 bus compatibility and dual-channel clock independence, but requires external level shifters for RS-232.
Availability
SCC68692C1N40,602 is available at Aetrix Electronics and suitable for industrial terminal systems, embedded controller communication, legacy equipment emulation, and test & measurement instrumentation requiring stable component supply, long-lifecycle support, and guaranteed availability for production programs.
Supply support for SCC68692C1N40,602 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company formed from the spin-off of Philips Semiconductors in 2006, specializing in secure connectivity solutions, automotive electronics, and industrial control ICs.
The SCC68692C1N40,602 belongs to NXP's legacy communications interface product line, designed specifically for robust, long-lifecycle embedded serial communication in industrial automation, point-of-sale, and instrumentation applications requiring parallel-bus UARTs with advanced timing and control features.
FAQ
What is the maximum baud rate supported by the SCC68692C1N40,602?
The SCC68692C1N40,602 supports standard baud rates up to 115.2 kbaud per channel using its internal baud rate generator with a 3.6864 MHz crystal. Non-standard rates up to 115.2 kbaud are achievable via the 16-bit counter/timer, and external 1X or 16X clock inputs allow operation beyond this limit depending on external timing source capability.
Is the SCC68692C1N40,602 pin-compatible with the SCN68681?
Yes, the SCC68692C1N40,602 is explicitly stated in its datasheet to be compatible with the SCN68681. It maintains identical pinout, register mapping, and S68000 bus timing, making it a direct replacement in existing designs - though it adds enhanced features like receiver timeout and multidrop wake-up mode not present in the SCN68681.
Does the SCC68692C1N40,602 include an on-chip crystal oscillator?
Yes, the SCC68692C1N40,602 integrates a crystal oscillator circuit. Pins X1/CLK and X2 are designed for direct connection of a 3.6864 MHz crystal; the oscillator provides the base timing reference for the baud rate generator, counter/timer, and internal logic - eliminating the need for an external clock source in most configurations.
How does the quadruple receiver buffering in the SCC68692C1N40,602 improve system reliability?
The quadruple receiver buffering in the SCC68692C1N40,602 provides four levels of depth in each channel's receive holding register chain. This significantly reduces the risk of receiver overrun during high-data-rate bursts or when CPU interrupt latency is variable, allowing more time for firmware to service interrupts before buffer overflow occurs - especially valuable in real-time industrial control applications.
Can the SCC68692C1N40,602 operate with different baud rates on Channel A and Channel B simultaneously?
Yes, the SCC68692C1N40,602 allows independent baud rate configuration for each channel. Each receiver and transmitter can select its clock source separately - from the shared baud rate generator, the 16-bit counter/timer, or external 1X/16X inputs - enabling true dual-speed operation, such as 9600 bps on Channel A and 38.4 kbaud on Channel B, without cross-interference.
What is the function of the 6-bit input port (IP0–IP5) on the SCC68692C1N40,602?
The 6-bit input port (IP0–IP5) on the SCC68692C1N40,602 serves dual roles: as general-purpose digital inputs or as dedicated control signals including CTSAN/CTSBN, RxCA/RxCB, TxCA/TxCB, and CTCLK. Four of these inputs (IP0–IP3) support change-of-state detection with interrupt generation, enabling efficient monitoring of external events without constant polling.
SCC68692C1N40,602 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 40-DIP (0.600", 15.24mm)
- Series:
- -
- Packaging:
- Tube
- Product Status:
- Obsolete
- Features:
- Configurable GPIO, Internal Oscillator, Timer/Counter
- Number of Channels:
- 2, DUART
- FIFO's:
- -
- Protocol:
- -
- Data Rate (Max):
- 1Mbps
- Voltage - Supply:
- 5V
- With Auto Flow Control:
- Yes
- With IrDA Encoder/Decoder:
- -
- With False Start Bit Detection:
- Yes
- With Modem Control:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 40-DIP
SCC68692C1N40,602 FAQ
1.How can I place an order for SCC68692C1N40,602 through Aetrix?
Please submit a Request for Quotation (RFQ) for SCC68692C1N40,602 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SCC68692C1N40,602 reliable?
The price and inventory of SCC68692C1N40,602 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SCC68692C1N40,602 is usually 5 days.
3.What payment methods are accepted for SCC68692C1N40,602?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SCC68692C1N40,602 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SCC68692C1N40,602?
SCC68692C1N40,602 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SCC68692C1N40,602 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SCC68692C1N40,602?
For technical support, including SCC68692C1N40,602 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SCC68692C1N40,602 requirements.
6.How does Aetrix verify that SCC68692C1N40,602 is sourced from the original manufacturer or authorized distributors?
All SCC68692C1N40,602 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SCC68692C1N40,602 meets industry standards.
7.What is the process for return or replacement of SCC68692C1N40,602?
All SCC68692C1N40,602 units undergo pre-shipment inspection (PSI). If there is an issue with SCC68692C1N40,602, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SCC68692C1N40,602 part is unused and in its original packaging.
Return procedure for SCC68692C1N40,602:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SCC68692C1N40,602 Tags
-
SC16IS741AIPWJ
NXP Semiconductors
-
TL16C550CPTR
Texas Instruments
-
TL16C550CIPTR
Texas Instruments
-
SC16C752BIB48,128
NXP Semiconductors
-
ST16C2550CQ48-F
MaxLinear, Inc.
-
ST16C2550CJ44-F
MaxLinear, Inc.
-
ST16C2552CJ44-F
MaxLinear, Inc.
-
ST16C1550IQ48-F
MaxLinear, Inc.
-
ST16C2550IQ48-F
MaxLinear, Inc.
-
ST16C554DIQ64-F
MaxLinear, Inc.
-
ST16C554DCQ64-F
MaxLinear, Inc.
-
XR17V352IB113-F
MaxLinear, Inc.
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
