Microchip Technology SCH3112I-NU
- Part No.:
- SCH3112I-NU
- Manufacturer:
- Microchip Technology
- Category:
- Specialized
- Package:
- 128-TQFP
- Datasheet:
-
SCH3112I-NU.pdf
- Description:
- IC INTFACE SPECIALIZED 128VTQFP
- Quantity:
- Payment:

- Shipping:

Inventory:1,979
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Product details
Overview
SCH3112I-NU from Microchip Technology is an industrial-grade LPC Super I/O controller integrating keyboard/mouse control, dual NS16550-compatible UARTs, IEEE 1284 EPP/ECP parallel port, 2.88MB floppy disk controller, hardware monitoring (voltage, temperature, fan), and programmable clock output. It operates at 3.3V with 5V-tolerant SIO block and supports PC99/PC2001 and ACPI 2.0 standards in embedded industrial motherboard designs.
For engineers reviewing the SCH3112I-NU datasheet, SCH3112I-NU pinout, SCH3112I-NU application, or SCH3112I-NU equivalent, this page delivers verified technical context, exact pin functions, real-world use cases in legacy-compatible industrial systems, and validated alternative parts for design continuity and supply resilience.
Technical Context
The SCH3112I-NU implements a full ISA Plug-and-Play register set (v1.0a) with up to 480 I/O address options and serialized IRQ support for PCI systems. Its LPC interface operates at 19–33 MHz and integrates legacy blocks including an 8042-compatible keyboard controller with 2 kB ROM and 256 B RAM, plus Phoenix BIOS ROM support.
Hardware monitoring includes four analog voltage inputs (+2.5V, +5V, +12V, Vccp), internal/external temperature sensing (±1.5°C accuracy), three fan tachometer inputs, three PWM outputs, and dedicated nHWM_INT and THERMTRIP outputs for out-of-limit event signaling and system shutdown coordination.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| LPC Bus Frequency | 19–33 MHz - Enables direct integration into modern low-pin-count motherboard architectures without bridge logic. |
| Serial Ports | 2 × NS16550-compatible UARTs - Each supports 16-byte FIFO, up to 1.5 Mbps baud, and RS485 auto-direction control. |
| Floppy Controller | CMOS 765B core - Provides 100% IBM PC/XT/AT software and register compatibility with vertical recording support. |
| Hardware Monitor Inputs | 4 voltage channels, 2 thermal diode inputs, 1 ambient sensor - Enables comprehensive power rail and thermal validation in headless industrial systems. |
| GPIO Count | 40 general-purpose I/O pins - Includes 6 VID-compatible inputs for processor voltage identification in x86-based platforms. |
| Package | 128-pin VTQFP (14×14×1.0 mm, 2 mm footprint) - RoHS-compliant surface-mount package suitable for automated PCB assembly. |
| Temperature Range | −40°C to +85°C - Qualified for uncontrolled industrial environments requiring extended thermal reliability. |
Pinout & Package
128-pin VTQFP RoHS-compliant package with 0.4 mm pitch, 14 mm × 14 mm body, and 1.0 mm height per Microchip Package Drawing DS00001730A-page 6.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| LPC_CLK | LPC Interface Clock Input | Accepts 19–33 MHz system clock; synchronizes all LPC transactions including configuration and data transfers. |
| LPC_FRAME# | LPC Bus Frame Signal | Active-low signal indicating start of LPC cycle; required for proper timing alignment with host chipset. |
| LPC_RST# | LPC Reset Input | Asynchronous reset for internal LPC logic; asserts device initialization without affecting other SIO subsystems. |
| nSMI | System Management Interrupt Output | Open-drain signal asserted on SMI events (e.g., keyboard wake, security key access); requires external pull-up. |
| nHWM_INT | Hardware Monitor Interrupt Output | Active-low open-drain interrupt signaling voltage/temperature/fan fault conditions to host CPU or EC. |
| THERMTRIP# | Over-Temperature Shutdown Output | Active-low pulse output triggered by programmable thermal threshold violation; used for immediate system reset or power-off. |
| CLKOUT | Programmable Clock Output | Configurable to 16 Hz - provides precise timing reference for RTC or watchdog timeout circuits. |
Key Features
| Feature | Design Value |
|---|---|
| ACPI 2.0 Compliance | Enables standardized OS-directed power management (S0–S5 states) and wake-event handling via PME interface. |
| Security Key Register | 32-byte write-protected register for device authentication - supports secure boot chain verification in trusted platform designs. |
| ChiProtect™ Parallel Port | Integrated overvoltage protection on all parallel port pins - eliminates need for external TVS diodes in printer or scanner interface applications. |
| Enhanced Digital Data Separator | Supports 250–2000 kbps floppy data rates with programmable precompensation - ensures reliable read/write across diverse media types and drive ages. |
| Power Button Control Logic | Dedicated circuitry for PS/2 keyboard power button debouncing and AC power failure recovery - reduces firmware complexity in embedded BIOS implementations. |
Applications
| Industrial Control Panel | Ruggedized Point-of-Sale Terminal |
|---|---|
Use Scenario: Fan-cooled PLC enclosure with serial-connected HMI, parallel-connected receipt printer, and local floppy-based firmware update capability. IC Role / Device Role / Timing Role: Central Super I/O hub managing UART communication, ECP printer interface, floppy boot loader, and real-time thermal/voltage supervision. Use Value: Single-chip consolidation replaces discrete UARTs, parallel transceivers, and monitor ICs - reducing BOM count and improving thermal margin via integrated fan PWM control. |
Use Scenario: Self-service kiosk operating in retail environments with intermittent AC power, requiring graceful shutdown on brownout and fast resume after power restoration. IC Role / Device Role / Timing Role: Power management coordinator providing AC fail detection, IDE/PCI reset assertion, and SMI-triggered BIOS recovery sequence. Use Value: Eliminates external power supervisor ICs and simplifies firmware handling of power events - enabling deterministic restart behavior after grid instability. |
| Legacy-Dependent Medical Instrument | Embedded Test Equipment |
Use Scenario: FDA-cleared diagnostic analyzer relying on IBM-compatible floppy boot media and PS/2 keyboard input for field calibration and service mode access. IC Role / Device Role / Timing Role: 8042 keyboard controller with Phoenix BIOS ROM, CMOS 765B floppy engine, and security key register for service authorization. Use Value: Maintains full backward compatibility with certified software stacks while adding modern hardware monitoring for predictive maintenance alerts. |
Use Scenario: Automated test fixture requiring high-reliability serial communication to DUTs, parallel-controlled switching matrix, and real-time voltage drift tracking during burn-in. IC Role / Device Role / Timing Role: Multi-function I/O concentrator delivering synchronized UART timing, EPP handshaking, and millivolt-level ADC monitoring via analog inputs. Use Value: Replaces separate UART, parallel port, and analog monitor ICs - ensuring traceable correlation between stimulus timing and measurement data across test cycles. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar Super I/O controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Winbond W83627DHG-P | 4 serial ports, no floppy controller, integrated SMBus host - lacks CMOS 765B core and vertical recording support. | Targeted at modern embedded systems without legacy floppy dependency; requires external FDC for boot-from-floppy functionality. | Select when prioritizing serial port count and SMBus connectivity over IBM-compatible floppy operation. |
| Nuvoton NCT6776D | 6 serial ports, no parallel port, no floppy controller - adds PCIe configuration space and enhanced GPIO routing. | Designed for newer chipsets lacking LPC legacy support; incompatible with PS/2 keyboard BIOS ROM requirements. | Choose for next-generation platforms migrating away from ISA-style peripherals and requiring PCIe-side configuration. |
Compared with SCH3112I-NU, W83627DHG-P offers higher serial port density but omits floppy control essential for legacy boot, while NCT6776D abandons parallel and floppy entirely in favor of PCIe integration - making SCH3112I-NU uniquely suited for industrial upgrades preserving full IBM PC/AT peripheral compatibility.
Availability
SCH3112I-NU is available at Aetrix Electronics and suitable for industrial control panels, ruggedized point-of-sale terminals, legacy-dependent medical instruments, and embedded test equipment requiring stable component supply across extended product lifecycles.
Supply support for SCH3112I-NU includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a U.S.-based semiconductor manufacturer specializing in microcontrollers, analog devices, and interface solutions for industrial, automotive, and communications markets.
The SCH3112I-NU belongs to Microchip's LPC Super I/O product line, designed specifically to consolidate legacy PC peripherals (keyboard, floppy, parallel, serial) and hardware monitoring into a single IC for cost-sensitive, long-lifecycle industrial motherboards.
FAQ
What is the maximum supported baud rate for the serial ports on the SCH3112I-NU?
The SCH3112I-NU features two NS16550-compatible UARTs supporting data rates up to 1.5 Mbps. This is achieved using its programmable baud rate generator and 16-byte transmit/receive FIFOs, enabling high-throughput serial communication in industrial automation interfaces without CPU overhead.
Does the SCH3112I-NU include a built-in floppy disk controller, and what level of IBM compatibility does it provide?
Yes, the SCH3112I-NU integrates a licensed CMOS 765B floppy disk controller supporting 2.88 MB formats and vertical recording. It delivers 100% IBM PC/XT and PC/AT software and register compatibility, including overrun/underrun detection and sophisticated power control circuitry for reduced power consumption during idle states.
How many voltage rails can the SCH3112I-NU monitor, and which specific supplies are supported?
The SCH3112I-NU monitors four external voltage rails (+2.5V, +5V, +12V, and Vccp) plus internal supplies (VCC, Vbat, Vtr). All monitored values undergo limit comparison with programmable thresholds, and out-of-range conditions trigger the nHWM_INT signal for system-level alerting or automatic response.
Is the SCH3112I-NU compatible with ACPI 2.0, and what power management features does it enable?
Yes, the SCH3112I-NU is fully ACPI 2.0 compliant and supports multiple low-power-down modes. It enables OS-directed power state transitions (S0–S5), programmable wake-up events (PME), System Management Interrupt (SMI), and serial IRQ interface - allowing seamless integration into Windows and Linux power management frameworks.
What is the function of the Security Key Register in the SCH3112I-NU, and how is it accessed?
The SCH3112I-NU includes a 32-byte Security Key Register used for device authentication in secure boot or service authorization workflows. It is write-protected and accessible only through specific LPC configuration space registers, preventing unauthorized read or modification during normal system operation.
SCH3112I-NU Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 128-TQFP
- Packaging:
- Tray
- Product Status:
- Active
- Applications:
- Controller
- Interface:
- LPC
- Voltage - Supply:
- 3.3V
- Supplier Device Package:
- 128-VTQFP (14x14)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
SCH3112I-NU FAQ
1.How can I place an order for SCH3112I-NU through Aetrix?
Please submit a Request for Quotation (RFQ) for SCH3112I-NU on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SCH3112I-NU reliable?
The price and inventory of SCH3112I-NU are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SCH3112I-NU is usually 5 days.
3.What payment methods are accepted for SCH3112I-NU?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SCH3112I-NU transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SCH3112I-NU?
SCH3112I-NU orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SCH3112I-NU order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SCH3112I-NU?
For technical support, including SCH3112I-NU datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SCH3112I-NU requirements.
6.How does Aetrix verify that SCH3112I-NU is sourced from the original manufacturer or authorized distributors?
All SCH3112I-NU products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SCH3112I-NU meets industry standards.
7.What is the process for return or replacement of SCH3112I-NU?
All SCH3112I-NU units undergo pre-shipment inspection (PSI). If there is an issue with SCH3112I-NU, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SCH3112I-NU part is unused and in its original packaging.
Return procedure for SCH3112I-NU:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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