My Inquiry
My Account
Microchip Technology SCH3112-NU
- Part No.:
- SCH3112-NU
- Manufacturer:
- Microchip Technology
- Category:
- Specialized
- Package:
- 128-TQFP
- Datasheet:
-
SCH3112-NU.pdf
- Description:
- IC INTFACE SPECIALIZED 128VTQFP
- Quantity:
- Payment:
- Shipping:
Inventory:2,588
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SCH3112-NU from Microchip Technology is a 128-pin VTQFP Super I/O controller with LPC interface, supporting PC99/PC2001 and ACPI 2.0 standards. It integrates an 8042-compatible keyboard controller, two NS16550A UARTs (1.5 Mbps), IEEE 1284 EPP/ECP parallel port, 2.88 MB floppy disk controller, hardware monitoring (voltage, temperature, fan), and programmable clock output to 16 Hz - deployed in legacy-compatible industrial motherboards and embedded x86 systems.
For engineers reviewing the SCH3112-NU datasheet, SCH3112-NU pinout, SCH3112-NU application, or SCH3112-NU equivalent, this page delivers verified functional scope, LPC bus timing (19–33 MHz), GPIO count (40 pins), VID-compatible inputs (6), and RoHS-compliant VTQFP package details essential for motherboard bring-up, BIOS integration, and long-life industrial design continuity.
Technical Context
The SCH3112-NU implements a unified LPC host interface compliant with Intel's Low Pin Count specification at 19–33 MHz, enabling direct replacement of ISA-based Super I/O functions while maintaining full register-level compatibility with legacy 8042, CMOS 765B floppy, and NS16550 UART firmware stacks. Its hardware monitor block accesses +2.5V/+5V/+12V/Vccp/VCC/Vbat/Vtr via four analog inputs and supports dual thermal diode sensing with ±1.5°C accuracy.
Power management includes SMI, PME, serial IRQ, and programmable wake-up events; reset logic provides IDE/PCI reset outputs and nRSMRST generation. The device excludes the four-pin serial ports and IDE/PCI reset disable found in SCH3116, confirming its role as the base two-serial-port variant within the SCH3112/SCH3114/SCH3116 family.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| LPC Bus Frequency | 19–33 MHz - defines maximum host-to-SIO command throughput and latency for configuration and data transfers. |
| Serial Ports | 2 × full-function NS16550A UARTs - each with 16-byte FIFO, up to 1.5 Mbps baud, and RS485 auto-direction control. |
| Floppy Controller | CMOS 765B core - 100% IBM PC/XT/AT software and register compatible, with 16-byte FIFO and vertical recording support. |
| Hardware Monitor Inputs | 4 voltage channels (+2.5V, +5V, +12V, Vccp) + 3 internal supplies (VCC, Vbat, Vtr) + 2 thermal diodes - enables full system power health visibility. |
| GPIO Count | 40 general-purpose I/O pins - includes 6 VID-compatible inputs for CPU voltage identification in desktop/server platforms. |
| Package | 128-pin VTQFP (14×14×1.0 mm, 2 mm footprint) - RoHS-compliant surface-mount package with standard thermal and mechanical mounting requirements. |
| Operating Temperature | 0°C to +70°C (Commercial grade) - validated for use in non-extended-temperature industrial and commercial motherboard environments. |
Pinout & Package
128-pin VTQFP (Very Thin Quad Flat Package), 14 mm × 14 mm body, 1.0 mm height, 0.4 mm lead pitch, RoHS-compliant. Package outline conforms to Microchip drawing #00000029 (128VTQFP).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| LPC_CLK | LPC Interface Clock Input | Accepts 19–33 MHz system clock; synchronizes all LPC read/write transactions between host and SCH3112-NU. |
| LPC_FRAME# | LPC Bus Frame Signal | Active-low signal indicating start/end of LPC transaction cycle; required for protocol handshaking. |
| LPC_RST# | LPC Reset Input | Asynchronous reset input that clears internal configuration registers and places device in default boot state. |
| nLPC_AD[0:3] | LPC Address/Data Multiplexed Bus | 4-bit multiplexed address/data bus used for configuration space access and legacy I/O port mapping (up to 480 addresses). |
| nHWM_INT# | Hardware Monitor Interrupt Output | Open-drain active-low interrupt signaling out-of-limit voltage, temperature, or fan tachometer conditions to host. |
| THERMTRIP# | Over-Temperature Shutdown Output | Active-low pulse output triggered on programmed thermal threshold breach - used for system reset or forced shutdown. |
| KBCLK / KBDAT | Keyboard Clock/Data Lines | Bi-directional PS/2 interface signals for 8042-compatible keyboard/mouse communication. |
| UART1_TXD / UART1_RXD | Serial Port 1 Transmit/Receive | Dedicated TTL-level UART signals supporting full-duplex operation at up to 1.5 Mbps. |
Key Features
| Feature | Design Value |
|---|---|
| ACPI 2.0 & PC99/PC2001 Compliance | Enables seamless integration into legacy BIOS and UEFI firmware stacks without custom power-state patching. |
| Programmable Clock Output (16 Hz) | Provides precise low-frequency timing reference for RTC or watchdog timer synchronization without external crystal. |
| Security Key Register (32-byte) | Allows OEM-specific device authentication during POST or secure boot sequences - prevents unauthorized firmware substitution. |
| ChiProtect™ Parallel Port Protection | Integrated ESD and overvoltage protection on all parallel port pins - eliminates need for external TVS arrays in cost-sensitive designs. |
| Serial IRQ Sharing Support | Permits multiple serial ports to share a single system IRQ line - reduces interrupt resource contention in constrained x86 platforms. |
Applications
| Industrial Motherboard Control | Legacy BIOS-Compatible Embedded System |
|---|---|
Use Scenario: Fan-speed-controlled industrial PC motherboard with dual COM ports, parallel printer interface, and floppy boot capability. IC Role / Device Role / Timing Role: Central Super I/O hub managing keyboard/mouse, serial/parallel/floppy I/O, hardware monitoring, and reset generation. Use Value: Eliminates discrete glue logic and separate monitor ICs; supports full ACPI 2.0 power states and BIOS-standard register map for drop-in firmware compatibility. |
Use Scenario: Medical diagnostic equipment requiring long-term BIOS stability, PS/2 keyboard support, and thermal safety shutdown. IC Role / Device Role / Timing Role: Trusted legacy I/O controller providing 8042 keyboard interface, THERMTRIP#-driven emergency shutdown, and voltage margining alerts. Use Value: Enables certified Class II medical device compliance via deterministic thermal fault response and secure key storage for firmware integrity verification. |
| Embedded x86 Edge Gateway | Secure Boot Desktop Reference Platform |
Use Scenario: Fanless edge gateway using x86 SoC with LPC interface, requiring serial console, IR remote, and hardware health telemetry. IC Role / Device Role / Timing Role: LPC-attached peripheral manager delivering IrDA 1.0 infrared control, dual UART debug interfaces, and real-time voltage/temperature telemetry. Use Value: Provides standardized LPC-based telemetry path independent of SoC vendor - simplifies driver development and field diagnostics across product generations. |
Use Scenario: Desktop reference design validating secure boot chain with authenticated firmware loading and hardware-enforced root-of-trust. IC Role / Device Role / Timing Role: Secure I/O companion providing 32-byte Security Key Register for platform identity binding and SMI-triggered firmware validation hooks. Use Value: Enables OEM-specific cryptographic binding between BIOS, bootloader, and hardware - blocks unauthorized firmware reflashing in production environments. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar Super I/O controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Winbond W83627DHG-P | 128-pin LQFP; supports 4 serial ports, no IDE/PCI reset outputs; lacks ChiProtect™ and Security Key Register. | Targeted at cost-optimized consumer motherboards; no thermal diode support beyond ambient sensor. | Choose when higher serial port count is needed but security and advanced thermal monitoring are not required. |
| Nuvoton NCT6776D | 128-pin QFN; adds SMBus interface, enhanced PWM fan control, and integrated voltage regulator monitoring; no floppy controller. | Designed for modern UEFI platforms with no legacy floppy dependency; requires updated BIOS drivers. | Prefer for new designs where floppy support is obsolete and granular fan control is critical. |
Compared with SCH3112-NU, W83627DHG-P offers more serial ports but omits security and thermal diode features, while NCT6776D removes floppy functionality entirely but adds SMBus and finer-grained fan regulation - making SCH3112-NU uniquely suited for long-lifecycle industrial x86 systems requiring full legacy compatibility and hardware-enforced security.
Availability
SCH3112-NU is available at Aetrix Electronics and suitable for industrial motherboard control, legacy BIOS-compatible embedded systems, embedded x86 edge gateways, and secure boot desktop reference platforms requiring stable component supply across extended product lifecycles.
Supply support for SCH3112-NU includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a global semiconductor company specializing in microcontrollers, analog devices, and connectivity solutions, with leadership in embedded control and secure computing.
The SCH3112-NU belongs to Microchip's legacy Super I/O product line, designed specifically to replace aging ISA-based I/O controllers in x86 platforms while preserving full BIOS and OS driver compatibility through LPC interface and register-level fidelity.
FAQ
What is the primary function of the SCH3112-NU in an x86 system?
The SCH3112-NU serves as a fully integrated Super I/O controller that consolidates legacy PC peripherals - including keyboard/mouse (8042), floppy disk (CMOS 765B), dual serial ports (NS16550A), parallel port (IEEE 1284 EPP/ECP), hardware monitoring, and reset generation - onto a single LPC-connected device. Its register map and timing behavior ensure drop-in compatibility with existing BIOS and OS drivers, eliminating the need for discrete logic or FPGA glue in industrial and embedded x86 motherboards.
Does the SCH3112-NU support ACPI 2.0 power management features?
Yes, the SCH3112-NU is explicitly ACPI 2.0 compliant and implements System Management Interrupt (SMI), Programmable Wake-up Event (PME), serial IRQ, and multiple low-power-down modes via its sophisticated power control circuitry (PCC). These capabilities enable full integration into ACPI-defined sleep states (S1–S5) and allow the host system to manage power sequencing, wake events, and thermal throttling without external components.
How many serial ports does the SCH3112-NU provide, and what are their key capabilities?
The SCH3112-NU provides exactly two full-function NS16550A-compatible UARTs, each featuring 16-byte send/receive FIFOs, programmable baud rate generation up to 1.5 Mbps, RS485 auto-direction control, and support for IRQ sharing. Unlike the SCH3114 (4 ports) or SCH3116 (6 ports), the SCH3112-NU is the base variant optimized for cost-sensitive designs where only dual serial console or modem interfaces are required.
What hardware monitoring functions are implemented in the SCH3112-NU?
The SCH3112-NU monitors four external voltages (+2.5V, +5V, +12V, Vccp), three internal supplies (VCC, Vbat, Vtr), ambient temperature via internal sensor, and two external temperatures via thermal diode inputs (±1.5°C accuracy). It generates alerts via nHWM_INT# and THERMTRIP# outputs, supports programmable automatic fan control using three PWM outputs, and provides limit comparison and logging accessible over the LPC bus.
Is the SCH3112-NU pin-compatible with other members of the SCH311x family?
No - while the SCH3112-NU, SCH3114-NU, and SCH3116-NU share the same 128-pin VTQFP package and pinout for common signals (LPC interface, power, reset, clocks), functional pin assignments differ for serial port I/O, IDE/PCI reset outputs, and dedicated GPIOs. For example, SCH3112-NU exposes only two UART interfaces and includes IDE/PCI reset buffers absent in SCH3116-NU; therefore, PCB layout is not interchangeable across variants.
SCH3112-NU Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 128-TQFP
- Packaging:
- Tray
- Product Status:
- Active
- Applications:
- -
- Interface:
- LPC
- Voltage - Supply:
- 3.3V
- Supplier Device Package:
- 128-VTQFP (14x14)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
SCH3112-NU FAQ
1.How can I place an order for SCH3112-NU through Aetrix?
Please submit a Request for Quotation (RFQ) for SCH3112-NU on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SCH3112-NU reliable?
The price and inventory of SCH3112-NU are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SCH3112-NU is usually 5 days.
3.What payment methods are accepted for SCH3112-NU?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SCH3112-NU transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SCH3112-NU?
SCH3112-NU orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SCH3112-NU order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SCH3112-NU?
For technical support, including SCH3112-NU datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SCH3112-NU requirements.
6.How does Aetrix verify that SCH3112-NU is sourced from the original manufacturer or authorized distributors?
All SCH3112-NU products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SCH3112-NU meets industry standards.
7.What is the process for return or replacement of SCH3112-NU?
All SCH3112-NU units undergo pre-shipment inspection (PSI). If there is an issue with SCH3112-NU, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SCH3112-NU part is unused and in its original packaging.
Return procedure for SCH3112-NU:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SCH3112-NU Tags
-
NVT4857UKAZ
NXP Semiconductors
-
TCA8418RTWR
Texas Instruments
-
PCA9546APWR
Texas Instruments
-
MD0100N8-G
Microchip Technology
-
PCA9548APW,118
NXP Semiconductors
-
PCA9540BDP,118
NXP Semiconductors
-
PCA9548APWR
Texas Instruments
-
PCA9546APW,118
NXP Semiconductors
-
PTN3360DBS,518
NXP Semiconductors
-
PCA9546ABS,118
NXP Semiconductors
-
PCA9518PWR
Texas Instruments
-
PCA9545APW,118
NXP Semiconductors
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
