Microchip Technology SCH3114-NU
- Part No.:
- SCH3114-NU
- Manufacturer:
- Microchip Technology
- Category:
- Specialized
- Package:
- 128-TQFP
- Datasheet:
-
SCH3114-NU.pdf
- Description:
- IC INTFACE SPECIALIZED 128VTQFP
- Quantity:
- Payment:

- Shipping:

Inventory:2,615
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Product details
Overview
SCH3114-NU from Microchip Technology is a 3.3V LPC Super I/O controller with 5V-tolerant SIO block, featuring four NS16C550A-compatible UARTs (16-byte FIFO, up to 1.5 Mbps), IEEE 1284 EPP/ECP parallel port, IrDA 1.0 infrared interface, CMOS 765B floppy disk controller, and integrated hardware monitoring for +2.5V/+5V/+12V/Vccp/VCC/Vbat/Vtr supplies and dual thermal diode inputs - deployed in industrial embedded motherboards requiring legacy I/O consolidation.
For engineers reviewing the SCH3114-NU datasheet, SCH3114-NU pinout, SCH3114-NU application, or SCH3114-NU equivalent, key selection criteria include LPC bus timing compliance (19–33 MHz), 40 GPIOs with 6 VID-compatible inputs, IDE/PCI reset outputs, power button/AC fail recovery support, and industrial temperature range (−40°C to +85°C) in 128-pin VTQFP.
Technical Context
The SCH3114-NU implements an LPC interface compliant with PC99/PC2001 and ACPI 2.0 standards, supporting serialized IRQ, ISA Plug-and-Play register set, and four address options for power-on configuration. Its legacy blocks include an 8042-compatible keyboard controller with 2 kB ROM and 256 B RAM, plus Phoenix BIOS ROM support.
Hardware monitoring integrates three fan tachometer inputs, three PWM outputs, programmable automatic fan control, and nHWM_INT/Thermtrip outputs for voltage/temperature violation signaling. The watchdog timer generates configurable reset pulses, and the resume/main power good generator supports system-level power sequencing.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| LPC Bus Frequency | 19–33 MHz - ensures compatibility with Intel chipset-based motherboard designs requiring strict timing alignment. |
| Serial Ports | 4 × full-function NS16C550A UARTs - each with 16-byte TX/RX FIFO, RS485 auto-direction control, and IRQ sharing capability. |
| Floppy Controller | CMOS 765B core with 16-byte FIFO, vertical recording format support, and 100% IBM PC/XT/AT software/register compatibility. |
| Hardware Monitor Inputs | 4 analog voltage channels (+2.5V, +5V, +12V, Vccp) + internal VCC/Vbat/Vtr + dual thermal diode + ambient sensor - enables comprehensive system health telemetry. |
| GPIO Count | 40 general-purpose I/O pins, including 6 VID-compatible inputs - supports dynamic CPU voltage identification and board-level signal routing. |
| Package | 128-pin VTQFP (14×14×1.0 mm, 2 mm footprint) - RoHS-compliant surface-mount package with standard thermal and mechanical mounting characteristics. |
| Temperature Range | Industrial: −40°C to +85°C - qualified for deployment in uncontrolled environments such as factory automation and transportation systems. |
Pinout & Package
128-pin VTQFP (14×14×1.0 mm body, 2 mm footprint), RoHS-compliant, with exposed thermal pad per Microchip Package Outline DS00001730A-page 6.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| LPC_CLK | LPC Interface Clock Input | Accepts 19–33 MHz system clock; synchronizes all LPC transactions including configuration and data transfers. |
| LPC_FRAME# | LPC Bus Frame Signal | Active-low strobe indicating start of LPC cycle; required for proper timing of host-initiated read/write operations. |
| LPC_AD[0:3] | LPC Address/Data Multiplexed Bus | Time-multiplexed 4-bit bus carrying both address and data during LPC cycles; requires external latching logic. |
| nLPC_RST# | LPC Reset Input | Asynchronous active-low reset that clears internal LPC state machines and reinitializes configuration registers. |
| nHWM_INT# | Hardware Monitor Interrupt Output | Open-drain output asserted when monitored voltage/temperature/fan speed exceeds programmed thresholds. |
| THERMTRIP# | Over-Temperature Shutdown Output | Active-low pulse output triggered on programmable thermal violation; used to force system reset or power-down. |
Key Features
| Feature | Design Value |
|---|---|
| NS16C550A UARTs ×4 | Each supports 230k/460k/921k/1.5M baud with programmable divisor; eliminates need for discrete UART ICs in multi-serial designs. |
| IEEE 1284 Parallel Port | EPP 1.7/1.9 and ECP modes with ChiProtect™ circuitry - enables high-speed bidirectional peripheral interfacing while protecting against ESD events. |
| Integrated Hardware Monitor | Real-time voltage/temperature/fan telemetry with automatic PWM fan control - reduces BOM count and firmware complexity for thermal management. |
| Power Management Logic | IDE/PCI reset buffers, power button control, AC power failure recovery, and SMI/PME generation - consolidates motherboard glue logic into single chip. |
| Security Key Register | 32-byte write-protected register for device authentication - supports secure boot and platform identity verification in OEM systems. |
Applications
| Industrial Control Panel | Medical Diagnostic Equipment |
|---|---|
Use Scenario: Fan-cooled PLC rack with serial-connected sensors, parallel-printer diagnostics, and IR-based service port. IC Role / Device Role / Timing Role: Central Super I/O hub managing UART-based Modbus RTU communication, EPP printer interface, and real-time thermal/voltage supervision. Use Value: Eliminates discrete UARTs, parallel port controllers, and monitor ICs; enables single-chip support for legacy fieldbus, printing, and safety-critical thermal shutdown via THERMTRIP#. |
Use Scenario: Portable ultrasound unit requiring low-power serial debug, IR firmware updates, and battery-backed voltage monitoring. IC Role / Device Role / Timing Role: System I/O coprocessor handling IrDA 1.0 firmware uploads, UART console logging, and Vbat/Vccp health tracking during battery operation. Use Value: Integrates IR transceiver, serial debug port, and backup-supply monitoring - reduces PCB area and improves reliability over discrete solutions. |
| Ruggedized Point-of-Sale Terminal | Legacy-Interface Industrial Gateway |
Use Scenario: Retail kiosk with PS/2 keyboard/mouse, parallel receipt printer, and dual serial barcode scanners. IC Role / Device Role / Timing Role: Legacy I/O bridge providing 8042 keyboard/mouse control, EPP parallel port, and two UARTs for scanner interfaces. Use Value: Maintains full IBM PC/AT compatibility while enabling compact design - avoids FPGA or custom ASIC for legacy peripheral support. |
Use Scenario: DIN-rail gateway connecting Modbus RTU field devices (RS485) to Ethernet via ARM host, requiring watchdog and power-fail recovery. IC Role / Device Role / Timing Role: System supervisor providing watchdog reset, IDE/PCI reset buffering, and AC power failure detection with software-controlled response. Use Value: Ensures deterministic recovery from brownouts and hangs without host CPU intervention - critical for unattended remote deployments. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar Super I/O controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Winbond W83627DHG-P | Supports only 2 serial ports; lacks IDE/PCI reset outputs and AC power failure recovery logic. | Targeted at cost-sensitive consumer desktop boards rather than industrial systems requiring robust power management. | Select if lower pin count and reduced feature set suffice; verify absence of IDE/PCI reset requirement in target design. |
| Nuvoton NCT6776D | Includes integrated EC (Embedded Controller) functionality and USB 2.0 interface; no floppy controller or PS/2 keyboard ROM. | Designed for modern notebook platforms with USB-centric I/O; not suitable for PS/2 or FDD-dependent legacy systems. | Choose only when migrating from PS/2 to USB peripherals and requiring embedded controller services beyond basic Super I/O. |
Compared with SCH3114-NU, W83627DHG-P omits critical industrial features like IDE/PCI reset and AC fail recovery, while NCT6776D replaces legacy PS/2/floppy support with USB/EC functions - making SCH3114-NU uniquely suited for ruggedized designs retaining full IBM PC/AT compatibility.
Availability
SCH3114-NU is available at Aetrix Electronics and suitable for industrial control panels, medical diagnostic equipment, ruggedized point-of-sale terminals, and legacy-interface industrial gateways requiring stable component supply across extended product lifecycles.
Supply support for SCH3114-NU includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a U.S.-based semiconductor manufacturer specializing in microcontrollers, analog devices, and connectivity solutions for embedded systems.
The SCH3114-NU belongs to Microchip's legacy Super I/O product line, designed specifically to consolidate PC-compatible I/O functions - including keyboard/mouse, serial/parallel/floppy, IR, and hardware monitoring - onto a single LPC-connected IC for industrial and embedded motherboard applications.
FAQ
What is the maximum UART baud rate supported by the SCH3114-NU?
The SCH3114-NU supports UART data rates up to 1.5 Mbps using its NS16C550A-compatible UARTs. This is achieved through a programmable baud rate generator and 16-byte FIFOs, enabling high-throughput serial communication in industrial automation and diagnostic equipment where legacy RS232/RS485 interfaces remain essential. The SCH3114-NU maintains full register compatibility with industry-standard UART implementations.
Does the SCH3114-NU include a built-in floppy disk controller?
Yes, the SCH3114-NU integrates a licensed CMOS 765B floppy disk controller with 16-byte data FIFO, vertical recording format support, and 100% IBM PC/XT/AT software and register compatibility. It supports two floppy drives and includes sophisticated power control circuitry (PCC) with multiple powerdown modes. The SCH3114-NU retains this legacy function to enable continued use in repair, replacement, and specialized industrial systems still dependent on FDD interfaces.
What temperature ranges are available for the SCH3114-NU?
The SCH3114-NU is offered in two temperature grades: commercial (0°C to +70°C) and industrial (−40°C to +85°C). The industrial grade is explicitly documented in the datasheet and validated for operation across the full range, making it suitable for deployment in harsh environments such as factory floors, outdoor kiosks, and transportation systems. The SCH3114-NU part number suffix "I" denotes industrial grade, though the base SCH3114-NU is commercially rated unless otherwise specified.
How many GPIO pins does the SCH3114-NU provide, and what special functions do they support?
The SCH3114-NU provides 40 general-purpose I/O pins, six of which are VID-compatible inputs for dynamic CPU core voltage identification. These GPIOs support configurable pull-up/down, interrupt generation, and bit-wise direction control. They are used for board-level signal routing, LED control, status indication, and interfacing with external logic. The SCH3114-NU leverages these pins to replace discrete glue logic in motherboard designs requiring flexible I/O expansion.
Is the SCH3114-NU compatible with ACPI 2.0 and PC99/PC2001 specifications?
Yes, the SCH3114-NU is fully compliant with ACPI 2.0, PC99, and PC2001 specifications. It supports Programmable Wake-up Event (PME) signaling, System Management Interrupt (SMI), and Serial IRQ interface for PCI systems. This compliance ensures seamless integration into legacy and modern x86-based platforms requiring standardized power management, plug-and-play enumeration, and OS-directed configuration - a core requirement for the SCH3114-NU's target industrial motherboard applications.
SCH3114-NU Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 128-TQFP
- Packaging:
- Tray
- Product Status:
- Active
- Applications:
- -
- Interface:
- LPC
- Voltage - Supply:
- 3.3V
- Supplier Device Package:
- 128-VTQFP (14x14)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
SCH3114-NU FAQ
1.How can I place an order for SCH3114-NU through Aetrix?
Please submit a Request for Quotation (RFQ) for SCH3114-NU on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SCH3114-NU reliable?
The price and inventory of SCH3114-NU are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SCH3114-NU is usually 5 days.
3.What payment methods are accepted for SCH3114-NU?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SCH3114-NU transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SCH3114-NU?
SCH3114-NU orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SCH3114-NU order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SCH3114-NU?
For technical support, including SCH3114-NU datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SCH3114-NU requirements.
6.How does Aetrix verify that SCH3114-NU is sourced from the original manufacturer or authorized distributors?
All SCH3114-NU products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SCH3114-NU meets industry standards.
7.What is the process for return or replacement of SCH3114-NU?
All SCH3114-NU units undergo pre-shipment inspection (PSI). If there is an issue with SCH3114-NU, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SCH3114-NU part is unused and in its original packaging.
Return procedure for SCH3114-NU:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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