Microchip Technology SCH3221I-7U-TR

Overview

SCH3221I-7U-TR from Microchip Technology is a 3.3V (5V-tolerant) LPC-based Super I/O controller integrating four NS16550-compatible UARTs, dual IR ports (IrDA v1.2, HPSIR, ASKIR), 33 GPIOs, watchdog timer, two LED drivers, and programmable wake-up logic for ACPI-compliant PC systems. It supports up to 460 kbps serial data rates, 480 I/O address options per UART, and operates across industrial temperature range (−40°C to +85°C).

For engineers reviewing the SCH3221I-7U-TR datasheet, SCH3221I-7U-TR pinout, SCH3221I-7U-TR application, or SCH3221I-7U-TR equivalent, key selection criteria include LPC bus compatibility, UART FIFO depth (16-byte), IR protocol support (IrDA v1.2), VTR-powered wake capability, and 64-ball WFBGA package footprint constraints.

Technical Context

The SCH3221I-7U-TR implements a Low Pin Count (LPC) host interface compliant with Intel LPC Specification Rev 1.0, supporting Serial IRQ, ACPI SMI, and PME signaling. Its four UARTs are fully NS16550A-compatible with 16-byte send/receive FIFOs, programmable baud rate generators, and full modem control (nRTS/nCTS/nDTR/nDSR/nRI/nDCD).

Wake-up functionality is partitioned across power domains: VTR powers the PME block, WDT, LED2, CLKI32, and wakeup-capable GPIO inputs (GP11–GP13, GP16–GP17, GP20–GP23, GP30–GP37, GP40, GP50), enabling assertion of IO_PME# under VCC-off conditions. IR support includes dual physical IR ports with IRTX2/IRRX2 on GP21/GP20 and IRRX3 on GP22, plus IrDA v1.2 (4 Mbps), HPSIR, and Consumer IR modes.

Key Specifications

Pinout & Package

64-ball WFBGA package with 0.5 mm pitch; ball grid layout defined in Microchip DS00002120A, pages 7–9. Power domains: VCC (3.3 V main), VTR (3.3 V standby), VSS (ground), CLKI32 (32.768 kHz input), CLOCKI (14.318 MHz input).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar Super I/O controller applications.

Compared with NCT5577D and IT8786E, the SCH3221I-7U-TR uniquely delivers IrDA v1.2 (4 Mbps) with dual IR ports and VTR-powered wake logic - critical for medical, industrial, and kiosk designs requiring reliable low-power responsiveness and high-speed IR diagnostics.

Availability

SCH3221I-7U-TR is available at Aetrix Electronics and suitable for industrial HMI terminals, legacy PC-based data acquisition systems, medical diagnostic equipment, and point-of-sale kiosks requiring stable component supply, long-lifecycle assurance, and RoHS-compliant packaging.

Supply support for SCH3221I-7U-TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Microchip Technology is a global semiconductor company specializing in microcontrollers, analog devices, and interface ICs, with a strong heritage in embedded control and PC platform components.

The SCH3221I-7U-TR belongs to Microchip's Super I/O product line, designed specifically for x86-based embedded and industrial computing platforms requiring consolidated serial, GPIO, IR, and power management functions in a compact WFBGA package.

FAQ

What is the maximum baud rate supported by each UART in the SCH3221I-7U-TR?

The SCH3221I-7U-TR supports a maximum baud rate of 460 kbps per UART. This is achieved using its programmable baud rate generator and NS16550A-compatible architecture. All four UARTs share this capability, and the 16-byte FIFOs ensure reliable data transfer at these speeds without overrun errors in typical embedded applications.

Does the SCH3221I-7U-TR support wake-up from VTR-only power, and which signals trigger it?

Yes, the SCH3221I-7U-TR supports wake-up from VTR-only power. Valid triggers include UART ring indicator inputs (nRI1–nRI4), watchdog timer timeout, and 22 designated GPIOs (GP11–GP13, GP16–GP17, GP20–GP23, GP30–GP37, GP40, GP50). These signals assert the open-drain IO_PME# output to notify the chipset of a wake event.

How many IR protocols does the SCH3221I-7U-TR support, and how are they implemented physically?

The SCH3221I-7U-TR supports IrDA v1.2 (4 Mbps), HPSIR, ASKIR, and Consumer IR protocols. It implements two physical IR ports: one using GP21 (IRTX2) and GP20 (IRRX2), and a second using GP22 (IRRX3). The IRMODE pin selects between modes, and internal IR controller logic handles protocol encoding/decoding without host CPU intervention.

What is the function of the GP57/nDTR2 pin, and why is an external pull-down required?

The GP57/nDTR2 pin serves as Data Terminal Ready for UART2 or as a general-purpose I/O. An external pull-down resistor is mandatory because the pin floats during VCC power-on reset (POR); failure to pull it low may cause improper LPC memory cycle handling, leading to unpredictable system behavior or excessive current draw. This requirement is explicitly documented in Note 3-12 of the datasheet.

Is the SCH3221I-7U-TR pin-compatible with earlier SCH3xxx series Super I/O devices?

No, the SCH3221I-7U-TR is not pin-compatible with prior SCH3xxx devices. It uses a 64-ball WFBGA package, whereas earlier generations (e.g., SCH3112, SCH3114) use 128-pin or 100-pin QFP packages. While register-level compatibility exists for many functions, PCB layout, power delivery, and signal routing must be redesigned for the WFBGA footprint and VTR power domain requirements of the SCH3221I-7U-TR.