NXP Semiconductors SE050F2HQ1/Z018HZ
- Part No.:
- SE050F2HQ1/Z018HZ
- Manufacturer:
- NXP Semiconductors
- Category:
- Specialized ICs
- Package:
- 20-XFQFN Exposed Pad
- Datasheet:
-
SE050F2HQ1/Z018HZ.pdf
- Description:
- IC PLUG/TRUST SEC ELEM 20HX2QFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SE050F2HQ1/Z018HZ from NXP Semiconductors is a Common Criteria EAL6+ certified secure element IC designed as an auxiliary security co-processor for IoT systems. It functions as an I²C target (3.4 Mbit/s) and I²C controller (400 kbit/s), provides 50 kB secured user flash, supports RSA/ECC/SHA/AES cryptographic suites, and enables secure credential injection, cloud onboarding, and Matter-ready device authentication in industrial (-40 °C to 105 °C) environments.
For engineers reviewing the SE050F2HQ1/Z018HZ datasheet, SE050F2HQ1/Z018HZ pinout, SE050F2HQ1/Z018HZ application, or SE050F2HQ1/Z018HZ equivalent, this page delivers verified technical context, validated pin roles, real-world use-value mapping, and confirmed alternative options - all grounded in NXP's official SE050 Rev. 3.8 product data sheet and ordering documentation.
Technical Context
The SE050F2HQ1/Z018HZ implements NXP's Integral Security Architecture 3.0™ with Java Card OS 3.0.5 and pre-installed IoT applet, enabling autonomous secure object management (symmetric/ECC/RSA keys, HMAC, binary files) under fine-grained access control policies. It supports dual concurrent secure messaging sessions and self-authenticated APDUs for multi-tenant ecosystems.
It features two independent I²C interfaces: one high-speed target (3.4 Mbit/s, address 0x48) for host MCU communication, and one fast-mode controller (400 kbit/s) for secure sensor interfacing - both active simultaneously. Its contactless ISO14443-A interface (56 pF resonance) and optional ISO7816 support are enabled per variant configuration; for SE050F2, ISO7816 is not enabled by default.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Security Certification | Common Criteria EAL6+ (HW + JCOP), FIPS 140-2 Level 3 (OS/Applet), Level 4 physical security |
| Cryptographic Support | RSA up to 4096-bit; ECC NIST/Brainpool/Edwards/Montgomery/Curve448; AES-128/192/256; SHA-1/224/256/384/512 |
| User Memory | 50 kB secured flash memory with 100M write cycles / 25-year retention |
| I²C Interfaces | Target mode: High-Speed (3.4 Mbit/s); Controller mode: Fast Mode (400 kbit/s); both active concurrently |
| Operating Temperature | -40 °C to +105 °C (confirmed by 'g=2' in part number and Table 9) |
| Supply Voltage | 1.62 V to 3.6 V (characterized range); max 6 V absolute limit |
| Power Modes | Power-down (<500 µA, state retained); Deep Power-down (<5 µA, no state retention, enabled via ENA pin) |
Pinout & Package
SE050F2HQ1/Z018HZ uses the HX2QFN20 plastic package (3 mm × 3 mm × 0.32 mm, 0.4 mm pitch), with thermal pad recommended to be connected to ground. Pin functions align with the SE050 platform's standardized HX2QFN20 pinning (SOT1969-1).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| I2C_SDA (Pin 9) | I²C Target Data Line | Primary host interface data line (3.4 Mbit/s); internal weak pull-up; referenced to VIN |
| I2C_SCL (Pin 10) | I²C Target Clock Line | Primary host interface clock line; internal weak pull-up; referenced to VIN |
| ENA (Pin 11) | Deep Power-down Enable | Pull low to enter <5 µA deep sleep; pull high to exit; required for Deep Power-down mode activation |
| VIN (Pin 12) | Logic & Interface Supply Input | Supplies I²C pads, ISO14443/ISO7816 logic; must power VCC via VOUT when Deep Power-down used |
| ISO14443 LA (Pin 17) | Contactless Antenna Terminal A | Connects to external NFC antenna coil; if unused, tie to VSS |
| ISO14443 LB (Pin 1) | Contactless Antenna Terminal B | Completes antenna loop; if unused, tie to VSS |
| VOUT (Pin 15) | Regulated Output Voltage | Provides regulated supply to VCC pad; mandatory connection for Deep Power-down operation |
| VCC (Pin 18) | Logic Supply Input | Must be connected to VOUT on PCB; supplies ISO7816/ISO14443 circuitry and logic core |
Key Features
| Feature | Design Value |
|---|---|
| Matter Ready Cryptography | Pre-integrated ECDSA, ECDH, and secure messaging channels required for Matter certification compliance |
| SCP03 Protocol Support | Enables bus encryption and encrypted credential injection to securely bind host MCU to SE050F2HQ1/Z018HZ at manufacturing |
| Dual I²C Roles | Simultaneous I²C target (host-facing) and I²C controller (sensor-facing) eliminates need for external bus switches or bridges |
| TRNG + DRBG | Fully compliant NIST SP800-90B TRNG and SP800-90A DRBG ensure cryptographically strong entropy for key generation and session keys |
| Secure Multi-Tenancy | Supports 2 concurrent secure messaging sessions plus default single-tenant session for flexible ecosystem deployment |
Applications
| Smart Home Device Authentication | Industrial Sensor Edge Security |
|---|---|
Use Scenario: Enabling Matter-compliant pairing of smart locks, thermostats, or lighting controllers with home hubs using zero-touch provisioning. IC Role / Device Role / Timing Role: SE050F2HQ1/Z018HZ acts as root-of-trust anchor, performing ECDH key exchange and ECDSA attestation during onboarding. Use Value: Eliminates manual credential entry; ensures cryptographic binding between device identity and cloud service, meeting CSA Matter specification requirements. | Use Scenario: Securing temperature, pressure, or vibration sensor data in factory automation before transmission to edge gateways. IC Role / Device Role / Timing Role: SE050F2HQ1/Z018HZ operates as I²C controller to read sensor registers, then signs/encrypts payloads using pre-provisioned ECC keys before forwarding to host MCU. Use Value: Prevents tampering with raw sensor values; enables end-to-end integrity and confidentiality without modifying sensor firmware or adding external crypto hardware. |
| Qi 1.3 Wireless Charging Auth | Cloud Onboarding for Asset Trackers |
Use Scenario: Authenticating power receivers (e.g., earbuds, wearables) to Qi 1.3 transmitters to prevent counterfeit charging and enable dynamic power negotiation. IC Role / Device Role / Timing Role: SE050F2HQ1/Z018HZ stores manufacturer-specific private keys and performs challenge-response authentication via ISO14443-A contactless interface. Use Value: Meets WPC Qi 1.3 security mandate; replaces discrete crypto ICs with single-chip solution supporting both contactless auth and secure storage. | Use Scenario: Provisioning AWS IoT Core or Azure Device Provisioning Service credentials into battery-powered GPS asset trackers during final test. IC Role / Device Role / Timing Role: SE050F2HQ1/Z018HZ serves as secure credential vault, injecting SCP03-encrypted keys into host MCU over I²C during production programming. Use Value: Enables zero-touch, scalable cloud registration; prevents exposure of private keys during manufacturing or field updates. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar secure element applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SE050E2HQ1/Z01Z3Z | Includes AES-CCM/GCM, GMAC, Curve448, and enhanced DRBG; same HX2QFN20 package and pinout | Required for applications needing authenticated encryption (e.g., Matter message encryption) or Curve448-based ECDH | Select SE050E2HQ1/Z01Z3Z when AES-GCM or Curve448 support is mandatory; otherwise SE050F2HQ1/Z018HZ suffices for standard Matter, Qi, and cloud onboarding. |
| STSAFE-A110 | CC EAL5+ certified; supports I²C only (no contactless); 32 kB secure memory; different pinout (8-pin SOIC) | Suitable for cost-sensitive, space-constrained designs where contactless/NFC is unnecessary and lower memory is acceptable | Choose STSAFE-A110 only if contactless interface and >32 kB memory are not required; verify I²C timing compatibility and layout redesign feasibility. |
Compared with SE050E2HQ1/Z01Z3Z, SE050F2HQ1/Z018HZ omits AES-GCM and Curve448 but retains full Matter readiness, Qi 1.3 support, and identical industrial temperature rating; versus STSAFE-A110, it offers higher memory, contactless capability, and stronger CC certification - at the cost of larger footprint and higher integration complexity.
Availability
SE050F2HQ1/Z018HZ is available at Aetrix Electronics and suitable for smart home device authentication, industrial sensor edge security, Qi 1.3 wireless charging authentication, and cloud onboarding for asset trackers requiring stable component supply across extended temperature ranges and long lifecycle commitments.
Supply support for SE050F2HQ1/Z018HZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT markets, with deep expertise in embedded security and trusted execution environments.
The SE050 platform was designed specifically to deliver plug-and-trust security for resource-constrained IoT endpoints - enabling rapid design-in of certified, future-proof cryptographic capabilities without custom firmware development.
FAQ
What security certifications apply to SE050F2HQ1/Z018HZ?
SE050F2HQ1/Z018HZ holds Common Criteria EAL6+ certification for both hardware and Java Card OS, and is FIPS 140-2 Level 3 certified for OS and applet functionality. Its physical security meets FIPS 140-2 Level 4 requirements. These certifications are validated per NXP's official documentation and apply directly to the SE050F2 variant as shipped.
Does SE050F2HQ1/Z018HZ support contactless communication out of the box?
Yes, SE050F2HQ1/Z018HZ includes native ISO14443-A contactless interface (56 pF resonance) with dedicated LA/LB antenna pins. It supports T=CL protocol for NFC reader interaction and is qualified for Qi 1.3 wireless charging authentication - no additional components or firmware are required to enable this functionality.
What is the maximum I²C clock frequency supported by SE050F2HQ1/Z018HZ in target mode?
SE050F2HQ1/Z018HZ supports I²C target mode at up to 3.4 Mbit/s in High-Speed mode when clock stretching is enabled - which is the default configuration for SE050F2 variants. If clock stretching is disabled (e.g., for host compatibility), the maximum frequency drops to 1 MHz.
Can SE050F2HQ1/Z018HZ operate as both I²C master and slave simultaneously?
Yes - SE050F2HQ1/Z018HZ integrates two independent I²C interfaces: one configured as a high-speed target (slave) for host MCU communication, and another as a fast-mode controller (master) for secure sensor interfacing. Both operate concurrently without conflict, enabling true dual-role operation on a single die.
Is ISO7816 interface enabled on SE050F2HQ1/Z018HZ by default?
No, ISO7816 interface is not enabled in generic SE050F2 configurations per NXP AN12436. Pins IO1, CLK, and RST_N remain functional only as GPIO or I²C controller lines unless explicitly enabled via custom configuration - which requires NXP engagement and is not part of the standard SE050F2HQ1/Z018HZ offering.
SE050F2HQ1/Z018HZ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 20-XFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- Plug and Trust Secure Element
- Applications:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-HX2QFN (3x3)
- Grade:
- -
- Qualification:
- -
SE050F2HQ1/Z018HZ FAQ
1.How can I place an order for SE050F2HQ1/Z018HZ through Aetrix?
Please submit a Request for Quotation (RFQ) for SE050F2HQ1/Z018HZ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SE050F2HQ1/Z018HZ reliable?
The price and inventory of SE050F2HQ1/Z018HZ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SE050F2HQ1/Z018HZ is usually 5 days.
3.What payment methods are accepted for SE050F2HQ1/Z018HZ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SE050F2HQ1/Z018HZ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SE050F2HQ1/Z018HZ?
SE050F2HQ1/Z018HZ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SE050F2HQ1/Z018HZ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SE050F2HQ1/Z018HZ?
For technical support, including SE050F2HQ1/Z018HZ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SE050F2HQ1/Z018HZ requirements.
6.How does Aetrix verify that SE050F2HQ1/Z018HZ is sourced from the original manufacturer or authorized distributors?
All SE050F2HQ1/Z018HZ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SE050F2HQ1/Z018HZ meets industry standards.
7.What is the process for return or replacement of SE050F2HQ1/Z018HZ?
All SE050F2HQ1/Z018HZ units undergo pre-shipment inspection (PSI). If there is an issue with SE050F2HQ1/Z018HZ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SE050F2HQ1/Z018HZ part is unused and in its original packaging.
Return procedure for SE050F2HQ1/Z018HZ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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