NXP Semiconductors SE97PW,118

Overview

SE97PW,118 from NXP Semiconductors is a JEDEC JC-42.4-compliant DDR memory module temperature sensor with integrated 256-byte SPD EEPROM, operating from −40 °C to +125 °C with ±1 °C max accuracy between +75 °C and +95 °C, 11-bit ΔΣ ADC resolution (0.125 °C), and I²C/SMBus interface - deployed on DIMMs for DRAM case temperature estimation and thermal throttling in DDR3 RDIMMs.

For engineers reviewing the SE97PW,118 datasheet, SE97PW,118 pinout, SE97PW,118 application, or SE97PW,118 equivalent, key selection considerations include its TSSOP8 package, 3.0–3.6 V supply range (EEPROM readable down to 1.7 V), programmable EVENT output polarity and hysteresis, SMBus TIMEOUT/ALERT support, and dual-function integration of JEDEC-grade thermal sensing and SPD memory for DDR3 memory modules.

Technical Context

The SE97PW,118 integrates a ΔΣ ADC-based temperature sensor and 256-byte serial EEPROM on a single die, sharing I²C/SMBus pins (SCL/SDA) and address pins (A0–A2) to enable up to eight devices per bus. Its EVENT output operates as open-drain with configurable polarity and supports comparator, interrupt, and critical-only modes via CONFIG register bits.

Temperature conversion occurs at ≥8 Hz (125 ms period), latching readings into a 16-bit temperature register; EEPROM is partitioned into lower 128 bytes (software write-protected) and upper 128 bytes (general-purpose), both supporting 100,000 write cycles and 10-year data retention.

Key Specifications

Pinout & Package

TSSOP8 package (SOT530-1), 8-lead, 4.4 mm body width, JEDEC-standard footprint for DIMM mounting.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar temperature-sensing-with-SPD applications.

Compared with SE98PW,118, the SE97PW,118 offers proven Grade B accuracy at lower cost for mainstream DDR3 RDIMMs, while AT30TS74-MA8M-T demands external memory and lacks JEDEC SPD integration - making SE97PW,118 the only solution meeting full JC-42.4 DIMM sensor + SPD requirements in a single TSSOP8 package.

Availability

SE97PW,118 is available at Aetrix Electronics and suitable for DDR3 RDIMM manufacturing, laptop memory module design, and enterprise server DIMM qualification requiring stable component supply and long-term JEDEC compliance support.

Supply support for SE97PW,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and communications markets.

The SE97PW,118 belongs to NXP's JEDEC-compliant thermal sensor product line, engineered specifically for DDR memory module integration with co-located temperature sensing and SPD EEPROM to meet JC-42.4 specifications.

FAQ

What is the primary function of the SE97PW,118 in DDR3 memory modules?

The SE97PW,118 serves as a JEDEC JC-42.4-compliant temperature sensor and integrated SPD EEPROM for DDR3 RDIMMs. It measures local DRAM temperature with ±1 °C max accuracy between +75 °C and +95 °C and stores vendor/module configuration data in its 256-byte EEPROM. This enables the memory controller to perform accurate thermal throttling instead of relying on worst-case ambient estimates - a capability critical for maintaining stability in high-performance laptops and servers using the SE97PW,118.

Does the SE97PW,118 support SMBus TIMEOUT and ALERT functions?

Yes, the SE97PW,118 fully supports SMBus TIMEOUT (default-enabled, resets internal state if SCL held low 25–35 ms) and SMBus ALERT Response Address (ARA) for interrupt arbitration. These features prevent system lockups and allow multiple SE97PW,118 devices on one bus to coordinate EVENT signaling without contention. The ARA is enabled by default and responds with its slave address upon host ARA polling - essential for reliable thermal event handling in complex DIMM configurations using the SE97PW,118.

What are the voltage requirements for reading and writing the EEPROM in the SE97PW,118?

The SE97PW,118 EEPROM operates with a write voltage range of 3.0–3.6 V and a read range of 1.7–3.6 V. This extended read capability allows SPD data access during low-power system states (e.g., S3 suspend) where VDD may drop below 3.0 V but remains above 1.7 V. Write operations require full 3.0–3.6 V supply to ensure reliable programming of the 256-byte memory - a design feature that maintains compatibility with DDR3 DIMM power sequencing while preserving SPD data integrity across the SE97PW,118's operational envelope.

How does the EVENT output of the SE97PW,118 behave in comparator versus interrupt mode?

In comparator mode, the SE97PW,118 EVENT output asserts continuously when temperature exceeds the upper alarm threshold or falls below the lower threshold - ideal for thermostat-style fan control. In interrupt mode, EVENT pulses once per threshold crossing and must be cleared via CONFIG register bit CEVNT before re-asserting. Critical temperature events override interrupt clearing: once T_crit is exceeded, EVENT stays asserted until temperature drops below T_crit - a safety-critical behavior confirmed in SE97PW,118's functional description and timing diagrams.

Can the SE97PW,118 be used on DDR2 modules, or is it DDR3-specific?

The SE97PW,118 is explicitly designed for DDR3 RDIMMs per JEDEC JC-42.4 and supports DDR2 modules as well, as confirmed in its Applications section and block diagram. Its 3.3 V operation, TSSOP8 footprint, and SPD EEPROM structure align with both DDR2 and DDR3 DIMM mechanical and electrical requirements. However, JEDEC JC-42.4 certification applies specifically to DDR3 mobile platform memory modules - meaning the SE97PW,118 meets the latest thermal sensor specification for DDR3 while maintaining backward compatibility with DDR2 implementations.