NXP Semiconductors SE97TP,128

Overview

SE97TP,128 from NXP Semiconductors is a JEDEC JC-42.4-compliant DDR memory module temperature sensor with integrated 256-byte SPD EEPROM, delivering ±1 °C accuracy from +75 °C to +95 °C, 11-bit ΔΣ ADC resolution of 0.125 °C, and I²C/SMBus interface (0–400 kHz) - deployed directly on SO-DIMM/UDIMM modules for DRAM case temperature estimation and thermal throttling control in thin-and-light notebooks.

For engineers reviewing the SE97TP,128 datasheet, SE97TP,128 pinout, SE97TP,128 application, or SE97TP,128 equivalent, this device supports critical DIMM-level thermal management including programmable upper/lower/critical trip points, reversible software write protection for SPD data, open-drain EVENT output with polarity selection, and SMBus TIMEOUT/ALERT compliance - all within a 2 mm × 3 mm HWSON8 package.

Technical Context

The SE97TP,128 integrates a local temperature sensor and 256-byte serial EEPROM on a single die, sharing I²C/SMBus pins (SCL/SDA) and address lines (A0–A2) to support up to eight devices per bus. Its 11-bit ΔΣ ADC performs conversions every 125 ms (8 Hz), latching results into a 16-bit temperature register with MSB-first transmission.

Thermal event signaling is implemented via an open-drain EVENT pin configurable as comparator (active HIGH/LOW window alarm) or interrupt mode, with hysteresis options (0/1.5/3/6 °C) and independent locking of UPPER/LOWER/CRITICAL thresholds. The EEPROM supports permanent/reversible write protection for lower 128 bytes (00h–7Fh), while upper 128 bytes (80h–FFh) remain freely writable for system-specific data.

Key Specifications

Pinout & Package

SE97TP,128 is housed in a 2 mm × 3 mm × 0.8 mm HWSON8 (SOT1069-1) thermally enhanced, leadless package with exposed pad for improved heat dissipation on DIMM PCBs.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar DDR memory module temperature sensing applications.

Compared with SE98TP,128, the SE97TP,128 offers JEDEC-validated Grade B accuracy optimized for DDR3 DIMMs at lower cost, while LM75BIMM-3/NOPB provides basic thermal sensing without SPD - making SE97TP,128 the only solution meeting both JEDEC thermal and SPD storage requirements in a single HWSON8 package.

Availability

SE97TP,128 is available at Aetrix Electronics and suitable for DDR3 memory modules, laptop thermal management systems, and enterprise server memory subsystems requiring stable component supply, JEDEC-compliant thermal telemetry, and integrated SPD EEPROM functionality.

Supply support for SE97TP,128 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and communication infrastructure markets.

The SE97TP,128 belongs to NXP's JEDEC-compliant thermal sensor product line, designed specifically to meet JC-42.4 Mobile Platform Memory Module Temperature Sensor requirements for DDR2/DDR3 DIMMs with integrated SPD functionality.

FAQ

What is the primary application of the SE97TP,128?

The SE97TP,128 is primarily used as a JEDEC JC-42.4-compliant temperature sensor and SPD EEPROM on DDR2/DDR3 memory modules. It measures DRAM case temperature to enable dynamic thermal throttling, replaces legacy Serial Presence Detect components, and stores vendor-specific memory module data in its 256-byte EEPROM - all within a single HWSON8 package optimized for DIMM edge mounting.

Does the SE97TP,128 support SMBus TIMEOUT and ALERT functions?

Yes, the SE97TP,128 fully supports SMBus TIMEOUT (25–35 ms SCL hold detection) and SMBus ALERT Response Address (ARA) functionality. TIMEOUT prevents system lock-ups by resetting the internal state machine, while ARA allows the SE97TP,128 to respond to host-initiated interrupt queries when configured in interrupt mode with active-LOW EVENT polarity - both features are enabled by default per JEDEC JC-42.4 requirements.

What are the voltage requirements for SE97TP,128 operation and EEPROM access?

The SE97TP,128 operates from 3.0 V to 3.6 V for full functionality including temperature sensing, EEPROM write, and EVENT output. EEPROM read operations remain functional down to 1.7 V, enabling reliable SPD data retrieval during low-voltage system states such as suspend-to-RAM, while shutdown current drops to 0.1 μA typical to minimize power draw.

How is the EVENT output configured on the SE97TP,128?

The EVENT output on the SE97TP,128 is an open-drain signal configurable via the Configuration register (CONFIG) for three modes: comparator (window alarm), interrupt (edge-triggered), or critical-only. Polarity (active HIGH/LOW), hysteresis (0/1.5/3/6 °C), and threshold locking are programmable. It requires an external pull-up resistor (0.9–3.6 V) and defaults to high-impedance at power-up to prevent spurious alarms.

What package type does the SE97TP,128 use and why is it suitable for DIMMs?

The SE97TP,128 uses the HWSON8 (SOT1069-1) package: 2 mm × 3 mm × 0.8 mm, thermally enhanced, leadless with exposed pad. Its compact size fits tight DIMM edge layouts, low profile avoids interference with memory sockets, and the exposed pad improves thermal coupling to the PCB - enabling accurate measurement of DRAM case temperature rather than ambient air temperature.