NXP Semiconductors SE98ATL,147
- Part No.:
- SE98ATL,147
- Manufacturer:
- NXP Semiconductors
- Category:
- Thermal Management
- Package:
- 8-XFDFN Exposed Pad
- Datasheet:
-
SE98ATL,147.pdf
- Description:
- IC TEMP SENSOR DDR 3.6V 8-HXSON
- Quantity:
- Payment:

- Shipping:

Inventory:1,388
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SE98ATL,147 from NXP Semiconductors is a JEDEC JC-42.4-compliant digital temperature sensor IC for DDR2/DDR3 memory modules, delivering ±0.5 °C (typ.) accuracy between +75 °C and +95 °C, 11-bit ΔΣ ADC resolution of 0.125 °C, and I²C/SMBus interface operation from 1.7 V to 3.6 V - deployed directly on DIMMs to monitor DRAM junction temperature in enterprise servers and laptops.
For engineers reviewing the SE98ATL,147 datasheet, SE98ATL,147 pinout, SE98ATL,147 application, or SE98ATL,147 equivalent, key selection considerations include its HXSON8 2 mm × 3 mm × 0.5 mm thermal-enhanced package, programmable EVENT output polarity and hysteresis (0 °C/1.5 °C/3 °C/6 °C), SMBus TIMEOUT/ALERT support, 8 Hz conversion rate, and JEDEC Grade B thermal specification compliance.
Technical Context
The SE98ATL,147 implements an on-die bandgap sensor feeding an 11-bit ΔΣ ADC updated at 8 Hz (125 ms conversion period), with internal registers for upper/lower/critical trip points, hysteresis configuration, and EVENT output mode selection (comparator or interrupt). Its SMBus TIMEOUT function resets the state machine if SCL is held low 25–35 ms, preventing bus lock-up across the full 1.7–3.6 V supply range.
Three address pins (A0–A2) enable up to eight devices on one bus; A0 is overvoltage-tolerant (10 V) for SPD-shared write protection. The open-drain EVENT output supports active-HIGH/active-LOW polarity, critical-only or window-based alarm modes, and SMBus ALERT arbitration - all configurable via the 16-bit Configuration register (01h) and trip-point registers (02h–04h).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Temperature Range | −40 °C to +125 °C operating range; ±1 °C max accuracy from +40 °C to +125 °C per JEDEC Grade B |
| Accuracy | ±0.5 °C (typ.) / ±1 °C (max.) between +75 °C and +95 °C - meets JEDEC TS3000B1 DIMM spec |
| Resolution | 0.125 °C (11-bit ΔΣ ADC output latched into 16-bit Temperature register) |
| Supply Voltage | 1.7 V to 3.6 V - enables direct integration with DDR module VDDQ rails |
| Interface Speed | I²C/SMBus compatible up to 400 kHz Fast-mode; SMBus TIMEOUT enabled by default |
| Quiescent Current | 250 μA (typ.) / 400 μA (max.) active; 0.1 μA (typ.) shutdown current |
| Hysteresis Options | Programmable via CONFIG[10:9]: 0 °C, 1.5 °C, 3 °C, or 6 °C - prevents oscillation near trip thresholds |
Pinout & Package
SE98ATL,147 is housed in an HXSON8 (SOT1052-1) package: plastic thermal-enhanced extremely thin small outline, no leads, 8 terminals, body dimensions 2 mm × 3 mm × 0.5 mm, compliant with JEDEC VCED-3 standard.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0 | I²C slave address bit 0 | Input with internal pull-down; overvoltage tolerant to 10 V for SPD software write protection |
| A1 | I²C slave address bit 1 | Input with internal pull-down; sets device address alongside A0/A2 (up to 8 devices/bus) |
| A2 | I²C slave address bit 2 | Input with internal pull-down; completes 3-bit hardware-selectable portion of 7-bit slave address |
| VSS | Ground reference | Device ground terminal; must be connected to system GND plane for accurate thermal measurement |
| SDA | I²C/SMBus data line | Open-drain bidirectional I/O requiring external pull-up; supports 0–400 kHz communication |
| SCL | I²C/SMBus clock line | Open-drain input requiring external pull-up; sampled at start of each bus access for address latching |
| EVENT | Thermal alarm output | Open-drain output configurable as active-HIGH/active-LOW comparator or interrupt; requires external pull-up (0.9–3.6 V) |
| VDD | Power supply | 1.7–3.6 V supply input; powers internal ADC, logic, and interface - no internal regulator |
Key Features
| Feature | Design Value |
|---|---|
| JEDEC JC-42.4 Compliance | Fully compliant with Mobile Platform Memory Module Thermal Sensor spec - validated for DDR2/DDR3 DIMM deployment |
| Configurable EVENT Output | Three operational modes: comparator (window-based), interrupt (edge-triggered), or critical-temp-only - selectable via CONFIG[0:2] |
| SMBus ALERT Support | Enables multi-device interrupt arbitration on shared SMBus; responds to Alert Response Address (ARA) when in interrupt mode |
| Robust Bus Interface | SMBus TIMEOUT prevents lock-up; hot-plug capable with 50 ns noise filtering; no driver conflict during power-up/down |
| Thermal Calibration | Factory-trimmed for ±0.5 °C (typ.) accuracy in 75–95 °C range; B-grade calibration stored in Capability register (00h = 0037h) |
Applications
| DDR Memory Thermal Monitoring | Laptop System Management |
|---|---|
Use Scenario: Mounted directly on DDR3 SO-DIMM PCB to track DRAM die temperature under sustained memory bandwidth load. IC Role / Device Role / Timing Role: Local temperature sensing node reporting real-time thermal data via I²C to platform controller hub (PCH) or baseboard management controller (BMC). Use Value: Enables dynamic memory throttling before JEDEC thermal limits are exceeded, preserving data integrity and extending module lifetime. | Use Scenario: Integrated into ultrabook motherboard near memory slots to provide thermal feedback for fan speed control and CPU DVFS coordination. IC Role / Device Role / Timing Role: Dedicated DIMM temperature monitor feeding thermal policy engine in embedded controller (EC) firmware. Use Value: Reduces system-level thermal margin requirements by 3–5 °C versus ambient-sensor-only approaches, enabling thinner chassis designs. |
| Enterprise Server DIMMs | Network Storage Memory Modules |
Use Scenario: Deployed on RDIMM/LRDIMM modules in 2U rack servers handling high-throughput database workloads. IC Role / Device Role / Timing Role: High-reliability thermal sentinel providing critical temperature alerts to BMC for predictive failure mitigation. Use Value: Supports JEDEC-defined critical trip point enforcement (e.g., 95 °C) with hysteresis to prevent false alarms during transient thermal spikes. | Use Scenario: Used in NAS memory modules where ambient airflow is restricted and localized DRAM heating exceeds ambient by >20 °C. IC Role / Device Role / Timing Role: Precision local sensor compensating for thermal gradient between memory ICs and board-level ambient sensors. Use Value: Eliminates need for conservative derating of memory speed/timing, maintaining rated bandwidth under constrained cooling conditions. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar temperature sensor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SE98APW,118 | TSSOP8 package (4.4 mm width); 0.8 mm height; lacks overvoltage-tolerant A0 pin | Better suited for prototyping or non-DIMM space-constrained boards where thermal enhancement is secondary | Select SE98APW,118 only when board layout allows larger footprint and SPD write-protection is not required. |
| SE98ATP,118 | HWSON8 package (2 mm × 3 mm × 0.8 mm); same pinout but 0.3 mm taller than SE98ATL,147 | Compatible with JEDEC VCED-3 but optimized for higher thermal dissipation in dense DIMM layouts | Choose SE98ATP,118 when thermal resistance to PCB is prioritized over minimal z-height in ultra-thin modules. |
Compared with SE98ATL,147, SE98APW,118 trades package miniaturization for ease of soldering and test access, while SE98ATP,118 offers improved thermal performance at the cost of 0.3 mm greater height - making SE98ATL,147 optimal for sub-0.6 mm z-height DDR modules requiring SPD write protection.
Availability
SE98ATL,147 is available at Aetrix Electronics and suitable for DDR3 server memory modules, laptop SO-DIMM thermal management, and enterprise network storage applications requiring stable component supply, JEDEC-compliant thermal accuracy, and long-term industrial lifecycle support.
Supply support for SE98ATL,147 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and communications markets.
The SE98A product line was engineered specifically for JEDEC-compliant DDR memory thermal monitoring, addressing the need for high-accuracy, low-power, SMBus-compatible sensors integrated directly onto DIMMs - with SE98ATL,147 representing the ultra-thin HXSON8 variant optimized for next-generation compact memory modules.
FAQ
What is the primary application target for the SE98ATL,147?
The SE98ATL,147 is specifically designed for JEDEC JC-42.4-compliant thermal monitoring on DDR2 and DDR3 memory modules. It is mounted directly on Dual In-Line Memory Modules (DIMMs) to measure DRAM junction temperature, enabling real-time thermal management in laptops, servers, and enterprise networking equipment. Its HXSON8 package and 2 mm × 3 mm footprint make it ideal for space-constrained DIMM layouts where minimal z-height is critical.
Does the SE98ATL,147 support SMBus TIMEOUT and ALERT functions?
Yes, the SE98ATL,147 fully supports both SMBus TIMEOUT and ALERT functions. SMBus TIMEOUT resets the internal state machine if SCL is held low for 25–35 ms, preventing bus lock-up - enabled by default across the full 1.7–3.6 V supply range. SMBus ALERT is active when the device is configured in interrupt mode with active-LOW EVENT polarity, allowing it to participate in multi-device interrupt arbitration via the Alert Response Address (ARA) protocol.
What are the accuracy specifications of the SE98ATL,147 over temperature?
The SE98ATL,147 delivers ±0.5 °C (typical) / ±1 °C (maximum) accuracy between +75 °C and +95 °C, meeting JEDEC TS3000B1 requirements. From +40 °C to +125 °C, accuracy is ±1 °C (typical) / ±2 °C (maximum); from −40 °C to +125 °C, it is ±2 °C (typical) / ±3 °C (maximum). These values reflect factory calibration and are stored in the Capability register (00h = 0037h for B-grade).
How is the EVENT output configured on the SE98ATL,147?
The EVENT output on the SE98ATL,147 is a configurable open-drain signal controlled via the Configuration register (01h). Its mode (comparator, interrupt, or critical-only) is set using bits [2:0], polarity (active-HIGH/active-LOW) via bit [1], and hysteresis via bits [10:9]. The output remains high-impedance at power-up until enabled (bit [3]), and supports external pull-up voltages from 0.9 V to 3.6 V - critical for interfacing with diverse host voltage domains.
What package type does the SE98ATL,147 use and what are its key mechanical features?
The SE98ATL,147 uses the HXSON8 package (SOT1052-1): a plastic thermal-enhanced extremely thin small outline package with no leads, 8 terminals, and dimensions of 2 mm × 3 mm × 0.5 mm. It complies with JEDEC VCED-3 standard and is optimized for minimal z-height on DDR modules. Unlike the TSSOP8 or HWSON8 variants, the HXSON8 provides the lowest profile while maintaining thermal performance and overvoltage-tolerant A0 functionality.
SE98ATL,147 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 8-XFDFN Exposed Pad
- Packaging:
- Cut Tape (CT)
- Product Status:
- Obsolete
- Function:
- Temp Monitoring System (Sensor)
- Sensor Type:
- Internal
- Sensing Temperature:
- -40°C ~ 125°C
- Accuracy:
- ±4°C(Max)
- Topology:
- ADC (Sigma Delta), Register Bank
- Output Type:
- I2C/SMBus
- Output Alarm:
- Yes
- Output Fan:
- Yes
- Voltage - Supply:
- 1.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-HXSON (2x3)
SE98ATL,147 FAQ
1.How can I place an order for SE98ATL,147 through Aetrix?
Please submit a Request for Quotation (RFQ) for SE98ATL,147 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SE98ATL,147 reliable?
The price and inventory of SE98ATL,147 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SE98ATL,147 is usually 5 days.
3.What payment methods are accepted for SE98ATL,147?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SE98ATL,147 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SE98ATL,147?
SE98ATL,147 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SE98ATL,147 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SE98ATL,147?
For technical support, including SE98ATL,147 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SE98ATL,147 requirements.
6.How does Aetrix verify that SE98ATL,147 is sourced from the original manufacturer or authorized distributors?
All SE98ATL,147 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SE98ATL,147 meets industry standards.
7.What is the process for return or replacement of SE98ATL,147?
All SE98ATL,147 units undergo pre-shipment inspection (PSI). If there is an issue with SE98ATL,147, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SE98ATL,147 part is unused and in its original packaging.
Return procedure for SE98ATL,147:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SE98ATL,147 Tags

-
EMC2101-ACZL-TR
Microchip Technology

-
MCP9844T-BE/MNY
Microchip Technology

-
EMC2101-R-ACZL-TR
Microchip Technology

-
MCP98244T-BE/MNY
Microchip Technology

-
TC670ECHTR
Microchip Technology
-
SE98ATP,547
NXP Semiconductors

-
AMC6821SDBQR
Texas Instruments

-
MAX6604AATA+T
Analog Devices Inc./Maxim Integrated

-
ADT7475ARQZ-REEL
onsemi

-
MAX6643LBBAEE+
Analog Devices Inc./Maxim Integrated
-
MAX6684ESA+T
Analog Devices Inc./Maxim Integrated

-
MAX6639AEE+
Analog Devices Inc./Maxim Integrated
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

